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    1,755 eigenfaces using fpga 找到的工作,价格在 HKD

    ...细节是用GPIO模仿Jtag烧录两片Xilinx的PROM. (XCF04S, XCF01S). Xilin有比较详细的方案。 见副件。 如果你们承接这类工程, 请你给我一个报价。 我们有硬件平台, 你们需要提供, 1 windows usb 的驱动, 指定等待下载的文件。 Cy7c68013A 的程序,把指定的文件烧录到目标PROM. 启动系统, 读取FPGA内部寄存器,确定烧录成功。

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    I am looking for people who join my team, we are working with new FPGA miner which are highly efficient that everybody can profit. basically it is a binary salery plan with a crypto mining product. So you have the chance to start your own business in the field or you work for me as a freelancer and get for every customer that signs up a reward of 25

    $275 - $2295
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    PCBA (FPGA) board design 21时 left
    已验证

    I need the design of PCBA/FPGA (Gerber file and BOM)

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    Following the sa...my categories to put inside my navigation menu on my ecommerce. The categories topics are: 1: Microcontrolers, Modules 2: Arduino, Raspberry pi, Tensilica, STM32, ATTINY, FPGA 3: Breadboard, Power Source, Network, Sensors, Modules, Relay (actuators), LED, CNC, Motor, USB, Memory, Infra-RED, Radio Frequency, Temperature, ASIC Chips

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    FPGA Card Programming 已经结束 left

    I am a cryptocurrency miner, and I would like to buy a larger number of FPGA cards to mine with, specifically the Xilinx VCU1525 FPGA Card. I need someone to Program the card to mine a number of specific algorithms. Preferably the dagger hashimoto, Neoscrypt, Equihash algorithms, I need a quote on how much this will cost.

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    i neeb vhdl project 已经结束 left

    i need vhdl project for fpga bord i need skeleton and can move

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    Need help developing a face detection system with the DE2-115 board and OV7670. I already developed the code for the face detection but in MatLab.

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    We are seeking a consultant to migrate several Xilinx K7, K7 Ultra and/or V7 FPGA-based DSP Apps (developed using Vivado) to OpenCL so they can run on Intel, AMD/ATI, NVIDIA and mobile GPUs. Ideally, the OpenCL acceleration would fit into our existing Windows / LabVIEW framework so we could have compatibility with our current set of apps.

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    write letter to customers 已经结束 left

    we sell our customers some IP (named CoaXPress FPGA IP). the price is one time however there is first year of maintenance and warranty provided free of cost with purchasing. Following years of maintenance are optional (not mandatory). However, if its not purchased, then customers will net get updates or support of their product. In case of requirement

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    fail during FPGA loading 已经结束 left

    I have a very simple FPGA project to test the Intel Arria 10 SoC Dev kit (DK-SOC-10AS066S-A) with Quartus Prime Pro 18.0 as follows. The main code instantiates an IOPLL Intel FPGA IP core to reduce the input board clock from 100 MHz down to 2 MHz which drives a Unique Chip ID core. It also blinks an LED on the board. You can download the project here:

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    i want to realize the transfer function on fpga so any one with knowledge of vhdl and quartus tool can bid Thank you

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    fpga for chris m 已经结束 left

    Designing an FPGA board for "5CEFA9F27I7N altera cyclone v". A board that include 4 ram sockets, full-size DIMM (desktop pc ram), DDR3. And programming an FPGA crypto miner for this board.

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    ...Kenntnisse in der Digital- / Analotechnik - Kenntnisse von Simulations- und Prüfumgebungen - Kenntnisse mit technischer Dokumentation/Nachweisführung. Technisch: - OrCAD, PSpice, FPGA/VHDL, C++ - DO-254, MIL-STD-1553...

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    Verilog program counter 已经结束 left

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

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    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

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    I am looking at an FPGA project using xilinx the project has very specific functions that i do not have the skills required to implement it myself sadly so i hope you can help with that. The project is for a crypto miner that can mine using the cryptonote algorithm Variant 1 i have chosen a model of FPGA as it has 100k logic gates and good memory

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    Hello I am doing a small project and am on the lookout for FPGA and software developer to work on a prototype. We are creating a product that is very similar to SmallHD monitors where we take a HDMI signal, process that signal and display that video signal plus overlays such as histograms, false colour and 3D LUTS. What we require for this prototype

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    FPGA programming 已经结束 left

    I am in need of an FPGA programmer for a Xilinix FPGA which I plan to mine cryptocurrencies with. If you have knowledge in this field I hope to hear from you.

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    ...serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e PT1 transfer function)

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    ...serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e PT1 transfer function)

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    Hi, I want to implement a CNN in a Xilinx FPGA using Caffe or Tensorflow.

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    ...freelancer to develop FPGA software alghorithm for Cryptonight V7 mining using Xilinx Virtex UltraScale+ FPGA VCU1525 card. Develop FPGA bitstream for mining Cryptonight v7 (CN7) algorithm on Xilinx Virtex UltraScale+ FPGA VCU1525 card + modify the miner software on PC to communicate with the FPGA. Miner software can communicate with FPGA card ...

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    FPGA circuit design 已经结束 left

    Need someone to do circuit design for an FPGA board. The board is being made from scratch. All we have so far is the FPGA chip.

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    $1962 - $5887
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    FPGA Algorimths 已经结束 left

    FPGA Algorimths, harware, software

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    The PONF Project ([login to view URL]) want to cre...are looking for an engineer that helps us design the electronics to control the Sony sensors to be connected to the Raspberry PI at the core of the project. We will be using Lattice FPGA to convert data. The requirement is to design the electronics, the relative PCB and create relative documentation.

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    Develop a musical bell that will play a selected and programmed song in the FPGA.

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    HPS-FPGA SDRAM bridge 已经结束 left

    ...DE1-SoC developmental board and I need a template project which allows me to transfer about 2kB of settings from the HPS side to the FPGA side. I want to use C on the HPS side to set 2048x 8-bit values which the FPGA can use to synthesize an arbitrary waveform in real-time. The memory can be SDRAM or any other suitable options available on the DE1-SoC

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    sensorless bldc motor 已经结束 left

    control a sensorless bldc motor using fpga

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    FPGA Mining 已经结束 left

    Mining Mining Mining Mining Mining Mining

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    Looking for a embedded Linux developer/engineer for developing a driver for an iMX6 module on a custom board for capturing 16-bit greyscale video supplied by an FPGA through the camera sensor interface on the IPU of the microprocessor. Must have previous experience with IPU drivers and camera interfacing, as well as driver development for embedded Linux

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    fpga programming 已经结束 left

    We are looking for a FPGA programmer, to build a mining software for Xilinx Virtex UltraScale+ FPGA VCU1525.

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    i am FPGA fan and , I try to setup connection between fpga device ( NetFPGA-1G-CML Kintex-7 ) and local computer . My main objective : simple comunication over ethernet cable . I have already done hardware design (in vivado) - microblaze core + TEMAC ([login to view URL]), which is verifed and works

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    I am looking for someone who can do RF layout and Digital layout. I am using 3 RX down-converters and 1 TX up-converter. I need to provide a LO to each of the RX chips (needs to be an wilikison divider). I need someone with the ability to design the divider and optimized miters and such. Each RC chip outputs I and Q signals (6 total) with are sent

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    1. Create a top level VHDL file for the project. VHDL code should be well formatted and commented. 2. Add two instantiations of a sync counter to the top level that are customized for the horizontal and vertical sync signals 3. Adapt the tesbench from homework 2 to simulate the top level file. Simulations should be annotated to depict events important to the operation of the design

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    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are exp...Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

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    Image encryption 已经结束 left

    I need image encryption using verilog on FPGA board

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    Develop and deliver FPGA code in vivado to: Take in attached NOAA wave file (IQ based) and decode it into a weather satellite image. This wave file was a recording of from NOAA satellite's Automatic Picture Transmission. The signal itself is a 256-level amplitude modulated 2400Hz subcarrier, which is then frequency modulated onto the 137 MHz-band

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    RISC processor using FPGA

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    RISC processor on FPGA

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    Designing of a pipeline processor which uses RISC like instruction set And implementation on fpga

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    "Need FPGA implementation of a Radar Matched Filter using Xilinx FPGA "

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    Altera FPGA DMA PCIe 已经结束 left

    I am looking for FPGA designer (Altera) with experience in DMA over PCIe.

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    hardware Design 已经结束 left

    vhdl code for wireless adhoc network and its implementation in FPGA,

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    I have to do video compression using FPGA(Field Programmable Gate Array) for a video recorder..

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    FPGA Image Processing 已经结束 left

    ...is already able to take pictures. We need a Zynq developer to write FPGA code that will process the pictures. We're using the Zynq 7010 clg225: [login to view URL] Specifically, we want streaming FPGA code that will: 1. Subtract the median-filtered image from the original

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    having some obstacles on monitor by using vga driver and an object will slide which will try not to crash a few obstacles

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    The...pixel is generated using an 8 bit counter whose first 3-bits are for red, next 3-bits are for green and last 2-bits are for blue color data while the synchronization signals are generated. This way, as the counter counts, 256 different color combinations are displayed on the screen one after another. This counter is implemented on the FPGA board

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    in the project there is a basic game. There are some walls placed vertically and an object slides and try to avoid crash these walls by using up and down buttons on FPGA. it is not mandatory to be a complex project. I need to have in a week.

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    Hi, I want a 2D convolution module in Verilog, using DSPs.

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