Eigenfaces using fpga工作

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    1,956 eigenfaces using fpga 搜到的工作,价格货币为 HKD

    ...细节是用GPIO模仿Jtag烧录两片Xilinx的PROM. (XCF04S, XCF01S). Xilin有比较详细的方案。 见副件。 如果你们承接这类工程, 请你给我一个报价。 我们有硬件平台, 你们需要提供, 1 windows usb 的驱动, 指定等待下载的文件。 Cy7c68013A 的程序,把指定的文件烧录到目标PROM. 启动系统, 读取FPGA内部寄存器,确定烧录成功。

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    Here projects are implemented in VHDL programming using Xilinx software. B.E/[登录来查看链接] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

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    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

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    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

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    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

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    Hi, I need a quick prototype of an Artix-7 fpga that makes a pcie to sd card controller (SD host controller/SD bus). Objective is to have a fpga card (working on pcie screamer) recognized as a SD/MMC card reader under windows, I need Windows to recognize/be able to install the windows built-in sd card drivers for the card. I don’t need it to actually

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    Hi Freelancers, I have a project I've been working on for the past 4 months- an Altera FPGA control system for a specific application. I’ve had the control system previously evaluated by an engineer, although there are aspects of the system I’d like to have double-checked prior to production. I’d like an Electrical Engineer to simply re-confirm my

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    We want a service of Fpga card design and embedded software

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    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (dow...SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

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    You have to programming a stopwatch with an Memory function in VHDL. It has to run on a Nexy 4 - fpga Board. Best regards, Kevin

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    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

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    I need a board that has HDMI input and output, and allows to overlay some picture on the top of the HDMI video stream. The p...example). Basically On-Screen display for HDMI. Need PCB to be designed and a prototype built. Important: please let me know how would you approach this problem, would you use FPGA or some type of ASIC, which part number etc.

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    FPGA and CMOS technology 已经结束 left

    FPGA and CMOS technology questions Just a few hours task Bit at hourly rate

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    Hi, Looking to make a small communication interface on FPGA board, Altera DE2-115. Not to lengthy task, just a 4 signal interface. Use Quartus. Communication interface name, XY2-100 Max time, 3 days.

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    Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. HI there, wondering if you ha...profile and would like to offer you my project. We can discuss any details over chat. HI there, wondering if you have the ability to create a bitstream for the XILINX VCU 1525 FPGA to mine cryptocurrency.

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    Project for JCSoft 12 小时 left

    Hello.. interested in a bitstream / miner for vu9p fpga card - VCU1525 -- let me know how much and if you can target equihash 150,5

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    Hi I am looking to offload a embedded system project which requires deep understanding of a) Hardware board design b) FPGA/RTL Developer c) Linux device driver expert d) software expert e) Signal processing expert

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    ...collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture WE PREFER: - Experience with HW synthesis tools for ASIC/FPGA - Knowledge of versioning tools (Git, SVN) - Ability to write clear and concise code - Active interest in the field and self-education - Interest in RISC-V or other architectures

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    The goal of the project is to translate an LCD bus with propriety signaling to drive a standard off the shelf LCD using RGB interface. In addition, the image will require interpolation while keeping the original aspect ratio. Source device will be provided + timing chart of source. Output LCD + LCD controller datasheet + init code will be provided

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    ...different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements, specs of FPGA, plan and execute

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    Lattice Ice40 FPGA coding 已经结束 left

    Looking for an experienced programmer in Lattice FPGA's, specifically the ICE40 series. Simple project, buffer 320 bytes of data with multiple clock domains. Prefer VHDL

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    I need you to develop Grin coin bitstream and provide miner compatible with BCU1525 FPGA.

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    VHDL or Verilog program 已经结束 left

    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

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    I got DE2 115 FPGA board and to implement the LOW pass filter using MATLAB simulink.

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    Bitstream Algo FPGA 已经结束 left

    I need you to develop bitstream algo (FPGA) for me. I would like this as soon as possible.

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    ...looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with reasonable

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    I have project with FPGA, need to read FPGA data which is driving LCD, after need to switch that data into VGA

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    Hi Freelancers, I have a project I've been working on for the past 2 months- an Altera FPGA control system for a specific application. Although I have knowledge in electrical engineering, I have no qualifications in the field, and thus I’d like a qualified individual to confirm my design, correct any mistakes I may have made, and possibly make the product

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    Hello I'm looking for a talented FPGA developer who have rich knowledge of mining with several kinds of algorithms and also have experience with it. Looking forward honest developers. Thanks

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    ...looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with reasonable

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    ...latency and power energy consumption so we can decide which suits us the best. Your tasks will include: • Investigating hardware optimization techniques targeting Xilinx FPGA Devices • Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate

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    Bug-fix/Update FPGA Miner 已经结束 left

    Bug-fix Mining App and FPGA-VHDL Project. You have to fix the mining App what is written in C and running on a Linux server. And fix on the FPGA side the PLL and add multicores.

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    Project for Feifei S. 已经结束 left

    ...required knowledge would have to be 1) FPGA bitstreams development 2) Crypto mining software. 3) You MUST have at least one VCU1525 (VU9P Xilinx board) AVAILABLE to be able to develop the bitstream. You will have to use an exhisting open source crypto minign software, developed for GPUs and CPUs, and port it to the FPGA in a VERY EFFICIENT way Very efficient

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    ...have to be 1) FPGA bitstreams development 2) Crypto mining software. 3) You MUST have at least one VCU1525 (VU9P Xilinx board) AVAILABLE to be able to develop the bitstream. The crypto mining software, already exhisting, should be ported to the FPGA in a VERY efficient way. Very efficient means that the hashrate output of the FPGA, once developed

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    Project for Volvox E. 已经结束 left

    Merhaba, bizim bir projede FPGA mühendisine ihtiyacimiz var ve sizinle bu konuda görüsmek istiyorum.

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    We are looking for developers/coders specialized in cryptos and blockchain for a project of firmware development. We would like to get a firmware to overclock this mining hardware i.e. graphic cards (GPU) RX580 8Go. Which are the maximum hashrates performances you can get?

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    Project for Eric D. 已经结束 left

    ...and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing

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    Project for Feifei S. 已经结束 left

    ...and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing

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    Project for Amir Y. 已经结束 left

    ...and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing

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    Project for Muhammad T. 已经结束 left

    Dear Muhammad, I am looking for an Hardware Engineer having experience with FPGA/ASIC in the Ethernet area. We want to build and develop a product and it looks that you would be able to do that. More details about the project I would share in the chat.

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    Project for Ahmed M. 已经结束 left

    ..."MagicNumber(2 bytes), Length(2 bytes), Payload(252 bytes)" 0xAA 0x55 , 0x00 0xFC , rest 252 bytes data 3. Main clock for FPGA is 50MHz. 4. Data read from FIFO is at main clock (50MHz). 5. Clock cross over should be handled without any data lose. 6. Timing contraints should be properly mentioned

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    more details will be given in the chat only serious expert and my maximum budget for this task is $100

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    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

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    We require a PCB designer familiar with gerber files and PCI Express FPGA designs. We have a reference design and we require the design simplifying so the board only provides the functions required to run our software as effective as possible.

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    Essay Writing 已经结束 left

    Hardw...artificial neural networks, machine vision and other machine learning algorithms for robotics, internet of things and other data-intensive or sensor-driven tasks. • SW, GPU, FPGA, ASICs, Heterogeneous computing • Examples: • Virtual machines and environments for NN acceleration • Nvidia Volta/Tesla application for NN acceleration Es

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    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [登录来查看链接]; a. The source can

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    ...for someone who can design a FPGA based x16r miner to mine Cuckoo Cycle based coins like rvn. The design should be adaptable for possible changes in the x16r algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with

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    find fpga projects 已经结束 left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

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