...细节是用GPIO模仿Jtag烧录两片Xilinx的PROM. (XCF04S, XCF01S). Xilin有比较详细的方案。 见副件。 如果你们承接这类工程， 请你给我一个报价。 我们有硬件平台， 你们需要提供， 1 windows usb 的驱动， 指定等待下载的文件。 Cy7c68013A 的程序，把指定的文件烧录到目标PROM. 启动系统， 读取FPGA内部寄存器，确定烧录成功。
Need to update VHDL and C-Code for change the communication from PCI-e to USB. The target is a Xilinx FPGA
We are Hiring Good Programmer in FPGA, GPU, CUDA, MATLAB for our Company. (Removed by Freelancer.com Admin)
The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact
...FPGAs with up to 3 types of physical RAMs (which may be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minimizes the area of the FPGA needed to fit each benchmark circuit....
...FPGAs with up to 3 types of physical RAMs (which may be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minimizes the area of the FPGA needed to fit each benchmark circuit....
...player's movement should not be pixel by pixel but rather, it should keep sliding until it hits the wall(boundary). The movement control should be done through the keys on the FPGA. The maze should have a fully functional non-flickering background, which should be easily be replaced. It should also have a start and game over screen. The work should have
I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players ro...imported from a library etc. The work should have lots of comments ,documentation and test (.do) files so that it can be easily understood by a beginner. it should work with a FPGA board.
I need an FPGA selected and hardware design created for decoding of an MPEG-Transport Stream parallel interface from a DVB-T demodulator. The FPGA needs to decode the transport stream and extract the video data as well as any other data contained in the Transport stream, the FPGA must then extract a selected individual pixel, and its colours are extracted
...you can modify that but I need the code running on FPGA board after I download it to it. Description: You have to create the VHDL model for the 4-bit multiplier. You must also synthesize the VHDL model, download to FPGA and test your multiplier on the FPGA board. Use a push button on the DE10-Lite FPGA to provide the clk input to the multiplier. The
This is a multi-part project for the Lattice MACHXO2-4000 LOGIC IC.
Looking for a developer to interface high speed TI DAC with virtex 7 FPGA. I am having DAC34H84 DAC and VC707 kit- and want to interface the same DAC with VC707 Hardware that i have is DAC34H84 and VC707
- schematic capturing; - PCB lay-outing; - production files generation, prototype bringing-up and troubleshoo...experience: mixed circuitry hardware design, digital interfaces: USB, ADC (120MHz), analog circuitry: impedance matching, ADC, frequencies up to 100MHz, clocking and sync schemes, FPGA/MCU and peripherals. Job Type: Contract Location: GTA
A simple boundary extraction project that involves eroding a binary image using morphological structuring element, and subtracting the outcome from the binary image to get boundaries.
We are a Signal processing Company, we are looking for designing a Board which can take 2 Channels of 70 MHz Input, 2 Channels of Baseband Signal 10 MHz BW, ... 2 Channels of Baseband Signal 10 MHz BW, 2 Digital TTL Channels with 10 MHz Rate and Ethernet Port for data transfer. All the Inputs and Outputs have to be connected to an FPGA processor Zync.
We are looking for one freelancer to develop FPGA software for best mining algo using Xilinx FPGA VCU1525 card. You will have to program an FPGA card that I will provide, to work for crypto mining. Is necessary also customize mining software that works under Windows to by able to works with the FPGA. Software must have to be perfectly optimized.
...found in attached files * * Program used : Quartus Prime * * Block Diagram template also found in attached files * * Hardware used: DE10-Lite kit with MAX10 10M50DAF484C7G FPGA * ____________ Final Products: ____________ -A software-level block diagram showing the connections between the System Verilog modules described in pdf -System Verilog implementations
1) Design a Finite State Machine (FSM) using Verilog to control the taillights of a 1965 Ford Thunderbird. 2) Implement your design on FPGA
... I currently need pcb layout engineer to upgrade my personal fpga board. It previously used Spartan 3E FPGA PQFP (PQ208/PQG208) package using the power voltage of 3.3v, 2.5v, 1.2v ... I'd like to have it replaced by an Artix fpga (FG484/FGG484 Fine-Pitch BGA package), henceforth using the lower voltages of 3.3v, 1.8v, 1.0v The voltage regulators are
I would like to port Nueral network for image identification on PYNQ FPGA
more details will be given in the chat and it more of writing article on this, if you cant write article on this please dont place your bid
The goal is to design a game on Xilinx FPGA. More details on chat. The deadline will be 3 days. Only serious bidders who can complete in 3 days should bid. No Excuses. Time wasters avoid bidding, please.
Cryptocurrency Mining Application in C or C++ We are seeking a senior engineer/architect with experience working with cryptocurrency mining sys...engineer/architect with experience working with cryptocurrency mining systems to provide technical consultation and to implement (or guide implementation) of a mining application for an FPGA via MicroBlaze.
FPGA, Embedded system writing and classification.
It is required to implement the lyra2z cryptographic algorithm on the FPGA. Series FPGA Ultrascale Kintex language Verilog. [登录来查看链接]
Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.
Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. It's about a Basys 3 FPGA control of an LCD, LED of the boards, a encoder and a ultrasonic sensor. please let me know if you can finish it in less than 2 days and in budget and we can discuss it
Hey, I have a project that needs to be done in Verilog and Vivado and I'll share details to anyone interested.
...connected to a PHY(PMA) IP, encoding the data with 8b10 protocol and then transmitting (no receiving) the data out through the PMA, 5Gbps. The data will be received by a Xilinx FPGA GTH Transceiver and then decoded. Therefore the PCS logics shall be compatible with the GTH Transceiver. Your tasks are 1. Write the PCS RTL code 2. Provide a compatible GTH
Design and development of non-invasive medical electronics devices that support and ...electronics devices that support and aid medical professionals in data acquisition and communication with expertise on processor/operating system/testing/system validation, FPGA design, integration of medical sensors, porting, middleware and application development.
Hi Loi L., I noticed your profile and would like to offer you my project. =================== The details : - my profile : fpga hobbyist newbie / singapore / currently working in a non-technology industry - hardware : - board : DE10-Lite MAX10 10M50DAF484C7G - monitor : HP Compaq LA2205wg, VGA mode 1680x1050-60Hz - OS : Linux distro (Linux
i have attached the document below. And i need this on 21st of october.
...developing a transmitter with digital modulation schemes with shorter delivery time. We developed all the algorithms required in LabVIEW FPGA. The same have to be ported to VHDL and be integrated before programming the Xilinx V6 FPGA on the transmitter. Complete hardware and many of the software blocks in VHDL are already built by our team. The requirement is
Need an expert in xilinx vivado Projects are based on digital systems on topics such as Multiplexers Flip flops registers Counters Clock dividers Please contact for project instructions and further details
I have my working model of neural network. I want to develop an accelerator on FPGA and show improvement in power.
...Video Production Landscape Design Online Writing Financial Analysis Drafting Package Design User Experience Design Moving Swift Autodesk Inventor Tattoo Design Call Center FPGA Handyman Microsoft SQL Server Digital Marketing Wikipedia Zbrush Carpentry Book Artist Procurement Database Development Raspberry Pi Wix VB.NET Sketching Email Developer Network
We are looking for someone who is very good with high speed digital layouts. The application is an Ethernet to digital audio motherboard. A daughter card with an Zynq FPGA/processor will install on this motherboard, and the motherboard will install onto a DAC board. There is a development board for this daughter card already. So this motherboard will
I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data
I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must
I need someone to modify the ccminer software. So it can communicate with FPGAs instead GPUs. It needs to work with both usb and pcie. I'm not asking for algorithm programming, I'm not asking for bitstreams. Just modifying the mining app ccminer so it works with FPGAs.
Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix
...expert in using MyRIO, MyRIO FPGA and MyRIO web services (Fig1 and 2). The project steps are explained as below: 1- The MyRIO should capture a signal (can be anything) with the sampling frequency of 5KHz. 2- Eleven (11) seconds of the signal must be captured. 3- I will provide you with two (2) MATLAB codes that must be run by MyRIO FPGA to analyse
Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.
Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant
...expert in using MyRIO, MyRIO FPGA and MyRIO web services (Fig1 and 2). The project steps are explained as below: 1- The MyRIO should capture a signal (can be anything) with the sampling frequency of 5KHz. 2- Eleven (11) seconds of the signal must be captured. 3- I will provide you with two (2) MATLAB codes that must be run by MyRIO FPGA to analyse
...complete this project. They both have sample projects for HDMI in and HDMI out. What I'm trying to accomplish is have: 1) PC->HDMI->FPGA->HDMI->Monitor 2) PC->USB-> FPGA 3) The PC will send information to the FPGA and create an overlay on the monitor. This software on the PC could be coded in C++ or C. Example, DrawText(x, y, "Truck #19 ready f...
We are looking for DSP Firmware Engineer who has specialized in algorithms' performance optimization for DSP/FPGA based on VLIW architecture.
I am looking to create hardware that will convert HDMI to NDI (Network Device Interface) I need both hardware and [登录来查看链接] is no set date when I need this by but w...HDMI to NDI (Network Device Interface) I need both hardware and [登录来查看链接] is no set date when I need this by but would like it soon. There is an sdk for the conversion by fpga.
...sent out of the FPGA chip through a single pin... Part 2 ...The serial transmission from part 1 is captured and converted to parallel data before being stored in another memory location( as 16 locations of 8-bits). The data in this memory should match with the data in memory in Part 1. Both parts are to be implemented in the same FPGA ....The serial
