Verilog vhdl工作

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    3,085 verilog vhdl 搜到的工作,价格货币为 HKD

    I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA

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    verilog design -- 2 6 天 left
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    I need to implement system verilog code design you will design a bit movement block. This block works with a 32 bit read and write interface, and can move data starting at any bit location. The block has two interfaces. One to read and write registers, another for the block to read and write memory, and a third interface for some status and completion information. The interface is defined with t...

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    verilog design 6 天 left

    I need to implement system verilog code design you will design a bit movement block. This block works with a 32 bit read and write interface, and can move data starting at any bit location. The block has two interfaces. One to read and write registers, another for the block to read and write memory, and a third interface for some status and completion information. The interface is defined with t...

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    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : fix neural network *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in training. *All of this should be printed in the ...

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    I am currently using Altera DE2-115 FPGA board to configure it using Quartus 17 lite edition software and write the code in VHDL. We have to use QSYS, and NIOS II for Eclipse to write a program in C and to run the board. I am seeking some help in building this mini thing.

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    We are seeking 1 FPGA Design Engineer for our new product development. FPGA Design Engineer Responsibilities: • Completing implementation in RTL • Ensuring robust and complete timing constraints • Optimizing FPGA code to balance performance, area, power, complexity and timing • Determining and executing development, integration, bring-up and test plans. • Working closely ...

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    hello, I am looking for expert who build GL algorithm using VHDL. If you can do it, we will discuss in details.

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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please, please.

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    Eye pupil tracking 15 小时 left

    I would like to do project in human eye pupil tracking system for video sequence using Verilog in Xilinx spartan 6 FPGA. Here with attached my equirements Requirements: 1. Find the pupil center coordinates and radius for various eye's. 2. Coordinates should be constant intervals while tracking. 3. Only video sequence to be used.... Not for image. Kindly send me possibility of above …...

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    i need a 8-bit comparator characterizing overdrive, to be implemented on FPGA, using Verilog also I need the constrains file

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    FPGA/VHDL/Verilog 已经结束 left

    Looking for implementation of a Ethernet Tester, generating and analyzing Ethernet traffic at 1G and 10G. More details on PM. J

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    BCD adder vhdl code which detects an overflow using vivado

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    Please read carefully. You need to fix my code. I will sent to you in messages my project. Here is project description: The brightness measurement with help of PMODALS sensor ([登录来查看链接] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([登录来查看链接]) is to be used, which takes over the control. The result of the brightness shoul...

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    Camera development 已经结束 left

    Opal Kelly front panel, C++, Verilog, XEM6010. Must have experience with Opal Kelly front panel, since this project will be similar with the EVB100X-DEV. Same concept, but different sensor.

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    GPS implementation 已经结束 left

    first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PCB of the board you have. U3 is ...

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    build opencl code 已经结束 left

    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : Build a deep neural network using some of approximate MAC UNIT, *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in traini...

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    Project for Rajagopal S. 已经结束 left

    Hi Rajagopal S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. The brightness measurement with help of PMODALS sensor ([登录来查看链接] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([登录来查看链接]) is to be used, which takes over the control. The result of the brightness should...

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    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : Build a deep neural network using some of approximate MAC UNIT, *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in traini...

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    Provide VHDL code and testbench simulation for ECP5 Lattice device (Diamond Studio) to read HX711 sample ([登录来查看链接]) And store it in 32bit register

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    Research help -- 3 已经结束 left

    Hello, this is the task: "first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PC...

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    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

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    I need vhdl code for signal processing. I need 256 point fir filter and 4096 point fft. create bid, many experience in signal processing. chatting discussing in detail

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    Need example code de-10 已经结束 left

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

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    Scope includes the programing (vhdl) for the measurement and of AC voltage, currents, Power (active, reactive and apparent power) and Power Factor in FPGA (Spartan-6). Interfacing ADC and sensors with FPGA for current and voltage measurements. It also includes the display of measured parameter on LED display which is inbuilt on board). This is the brief requirement, interested people may contact ...

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    More details will be shared via chat

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    More details will be shared via chat

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    Complex Signal Mixer VHDL 已经结束 left

    Design and Document a VHDL Complex Mixer • Design should contain two 11-bit complex NCOs (Numerically Controlled Oscillator): • Assume clock freq of 100MHz • NCO #1: 11MHz • NCO #2: 18MHz • Design a complex multiplier component • Multiply the outputs of NCO #1 and #2 • Write the outputs of the NCOs and Complex Multiplier to a text file Theory of operation Detai...

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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. (I need to fix my code only) I don't want imaginary freelancer, please.

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    Complete few tasks on Verilog software

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    Code on Verilog 已经结束 left

    Complete few tasks on Verilog software

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    Have several ways to effectively reduce sidelobe the ACAR. In order to overcome the contradictions of weight-based processing techniques and ensure high resolution, I intend to use the NLFM signal. I want to do all the processing with one FPGA without using any other block like DDS. There is an expectation that a signal generator for NLFM signal with resolution of 2 ^ 32 and FIR code for correspon...

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    Hey looking for some help with some introductory logic building using Verilog code on the vivado software. Also Its for basys3. It’s really elementary and if you know how to use vivado this should be quick and easy money for you. Thanks

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    Compile a verilog code 已经结束 left

    I need help in compiling a verilog code. I have already built a code that runs on a platform but when i run it on multisim, it gives me errors. I need an expert to guide me with this

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    Simplistic Matrix engine 已经结束 left

    I want to create a simple CPU the do some mathematics logic between two matrices using Verilog code

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    Hi, I need to emulate a crystal oscillator circuit (attached) based on wave digital filter (WDF). Basically we aim to have WDF emulation that match a Spice simulation (e.g. in Cadence). I Already have the circuit simulated in Cadence (the output attached) . Attached, my circuit (Crystal Oscillator) schematic that needs to be mapped to WDF along with its output waveform, you will notice that there ...

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    Project for Jin Q. 已经结束 left

    Hi Jin :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the val...

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    Project for Nick B. 已经结束 left

    Hi Nick :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the va...

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    Project for Jin C. 已经结束 left

    Hi Jin :) I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display..however my code is glitchy...if you could help me fix it it'd be a life...

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    Need to write VHDL program for Genesys 2 board for connecting a temperature sensor to xadc pin and display it in external LCD board

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    I have a task on verilog and i want someone who is experience on it to help me with it. Please bid only if you know youre an expert. I will share details with interested freelancer. Budget is limited, hiring will be on a weekly basis

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    Hi, I need a basic example of a state machine in VERILOG. We need to find the pattern "100" using machine states. We have 4 states: S0: Initial state S1: If 1 is found S2: If 0 is found S3: If 0 is found Encoding: S0: 00 S1: 01 S2: 11 S3: 10 Transition: Actual state / Input / Next state 00 - 0 - 00 00 - 1 - 01 01 - 0 - 11 01 - 1 - 01 11 - 0 - 10 11 - 1 - 01 10 - 0 - 00 10 - 1 - 01 T...

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    Handson training required on Xilinx Zc-702 including device programming in vhdl and its interfacing with perepherels like ADC, DAC, Memory etc.

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    I have problem in "fpga" I can't how to interface between power stage card and "fpga" card Can you write program in "vhdl" language?

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    Wanted Online FPGA Tutor 已经结束 left

    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

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    FPGA Development 已经结束 left

    More than 2 years of experience in FPGA design and development area. Candidate should have working Industry experience in below skill set:- •Working experience to process received frequency chirplet data using FPGA and to transmit processed data by interfacing FPGA with Radio Frequency (RF) transceiver module ADRV9009 and 10 Gigabit Ethernet Media Access Controller (10GEMAC). •Working ...

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    Needs to hire 3 Freelancers We are a small and growing company offering consulting and engineering services in many different areas of industry. Here you can find more about us: [登录来查看链接] In order to enforce our team, we are seeking embedded systems designers with experience in the following domains: * PCB design (Altium Designer, Eagle, KiCAD, PCAD...) * Firmware design (C/C++, assembler, Python...

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    Hi, We are looking for an experienced electronics engineer and software engineer, The project is to design a smart Home Cinema controller, the aim is to send data to a database, reading and writing data of different Video Projectors, Amplifiers, and many more devices via HDMI, USB, RS232, Ethernet, IR and many more. You will conceptualise the electronics and software for the system. We are stric...

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    Implemente un sistema de ecualización en tiempo real de tres bandas (bajos, medios y altos) en el FPGA de xilixn. Desarrolle los tres filtros necesarios para el ecualizador, los puede establecer en matlab o labview. Una vez definidos los coeficientes del filtro impleméntelos en el FPGA (a través de Matlab, Laview o Multisim). Se establece un bonus de 4 puntos para el grupo qu...

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    Build a neural network 已经结束 left

    Hi, I need : * ANN IN FPGA using my mac unit? *zybo-zynq-7000-arm-fpga-soc-trainer-board/ *verilog *MNIST

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