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    4,561 verilog vhdl 份搜到的工作,货币单位为 HKD

    Verilog FPGA Code implementation of FEC RS(198, 194) decoder.

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    I want go get help to implement FEC RS(198, 194)

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    vhdl expert 1 天 left

    I want Signal processing and VHDL(Quartus Application) expert.

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    5G RAN FPGA Design 已经结束 left

    We have an internal project for 5G RAN FPGA design for DFE products: Skills: Job Description- Senior MTS RTL design 5G Product( 2 positions) · Candidate must have at least Bachelors or Masters EE - FPGA design experience (RTL Coding, comms, DFE(DPD, DUC, DDC, FFT, FIR, CFR) · Candidate must have verifiable experience for a minimum 6 years as a Verilog/System Verilog/ VHDL/RTL programmer with extensive Verification test bench development experience · Preferred prior project experience in 5G ORAN - RU/DU. DSP knowledge Matlab modeling is preferred. · eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588 · Knowledge of Queuing theory · To...

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    I want you to desgin an IC chip description document. I need you to understand the verilog design and create some design descriotions, describing its fucntions in detail. The chip design has 3 main blocks ADC, PMU and sensors. These 3 blocks contain the most important functions of this chip. Please bid if you are experienced in wrting technical design documents for chip desing in detail. Thanks!

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    A presença de erros em dados digitais é um problema frequente em sistemas computacionais que lidam com transmissão e armazenamento de informação. Em alguns contextos, como o de computação aproximada, admite-se uma taxa ainda maior de erros para alcançar uma redução no consumo de energia. Nesses casos, torna-se imprescindível o controle de erro...controle de erros. Isto pode ser feito através do uso de códigos detectores (e corretores) de erros, que são capazes de detectar (e corrigir) a informação corrompida através de redundância inserida nos dados. Nesse projeto, o objetivo é gerar um codificador baseado em paridade e um detector de erros que avisa quando um...

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    the task is to develop and implement on synthesizable matrix multiplier kernels the simulation result compare with the result of matlab , the test platform read the input buffer of matrix A and B, then generating the output C. If the result is 100% compared with the result of matlab, the data in output file" OutputC .txt" should all appear true, otherwise , the result is false

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    I have the code for I2C slave. I want help in writing the verilog code for I2C Master testbench to communicate with the given slave. It can send a few i2C write and read commands (with address, data, etc). I have attached the code for I2C slave alonside for your reference.

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    1.VHDL code for SPI master to send data to a GPU. project setup for the customer's terasic FPGA board. assignment. demonstration of contents via zoom meeting. I will try to complete the project before the specified end date.

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    Your job is to write verilog code for i2c communication and interface it with a processor. Take data from the slave through the accelerator and store it in a memory. Make the processor read the data from that memory and give its response. Now write that response data back to the slave.

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    Hello everyone, I have to do a project in vhdl language. I have a list of 10/15 projects from which I have to choose one. The to-do list is: 1) report on the work done; 2) source code (in VHDL or other languages); 3) any examples for the code. The report typically consists of: - An overview of the topic. - A description of the methodology followed to carry out the project highlighting what are thought to be the most interesting contributions of the work done. - A high-level description of the code (it doesn't matter to put all the listings) and any instructions for use and compilation. - A description of the results obtained (simulations, statistics, algorithm outputs). I want to add that's not urgent.

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    SOC Verification 已经结束 left

    ...ARM Interconnects(AHB, APB), SPI, UART, I2C, DMA, Serial Flash, Security and Encryption. 3. Full chip SoC (C and SV based), Subsystem and Block/IP level verification. Test Bench generation with ability to run embedded C programs. Must have experience of 2-3 SoC verification. 4. Experience in HDL(Verilog, VHDL) and HVL(System Verilog, Specman) based functional verification. Experience in code coverage. 5. Experience in Verification methodologies(UVM, OVM and eRM). language simulation (Verilog-AMS, SystemVerilog). 7. Experience in Mentor, Cadence and Synopsys simulators. 8. Build automated Test bench and regression environments from a scratch. Should be able to write a test plan and generate test cases 9. Regression management and Verification Sign-off based o...

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    I need Verilog code for Energy-Efficient Logarithmic Square Rooter. It should be done within 1-2 days maximum.

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    the version of Vivado software is 2018.3. I could provide my project, I need someone to help modify my code to achieve correct function. the test data is produced by matlab, the correct result should the outputC file appear all true. it involves IP core and ram

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    I am looking to develop a Verification Code using System Verilog for USB 2.0 Protocol and also I want a verification plan for that . Kindly note that I want Complete TB code for all the components in Environment and also Test and Top instances as well . For any query/ or clarity ping me.

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    A complete color sorter Machine Firmware needs to be converted into Intel Quartus Project, The project contains IP Cores as well as softcore processor and the verilog coding part, All these to be integrated as a single bit file and to be implemented it on a Cyclone V FPGA Board.

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    We need a project done in Morse code encoder and decoder in VHDL. Our project contains 2 parts a transmitter and receiver. The transmitter part receives the text(ASCII) from the PC(user) via UART receiver and transmits the text to morse code encoder(converts text to morse code). The morse code pattern then is sent to an led. Dot(.) corresponds to LED on and dash(-) LED off. The receiver part has a photo diode which reads the blinking of the led(morse code) and data is transmits to Morse decoder where it is converted back to ASCII. The converted ASCII is then transmitted to end user PC for display. We have already designed the top level top level block diagram. we now need the source codes(entity and architecture) for the blocks and test benches for all blocks for simulation...

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    STM32 toolchain and also vhdl design with report describing the procedures

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    quartus and modulsim 已经结束 left

    i want some vhdl coding simulating with test bench on modulsim and a report

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    FPGA Project 已经结束 left

    I need to do simple FPGA project on Boolean Board (Real Digital). For example Tic Tac Toe game. software should be Vivado and programming should be done in Verilog.

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    This project requires basic knowledge of digital electronics and VHDL coding.

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    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

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    $163 - $543
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    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

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    $53 - $319
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    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

    $53 - $319
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    $53 - $319
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    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

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    Digital Electronics VHDL Program

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    Professional and proficient in the following areas Boolean Algebra and Logic Design  Number systems  Basic Theorems of Boolean Algebra  Canonical and Standard Forms  Logic Gate Implementations and Characteristics: ...Logic  Latches  Flip Flops  Finite-State Machine (FSM) Model  Synthesis and Analysis  Designing State Machines using State Diagrams  Designing State Machines using ASM (Algorithmic State Machine) Charts  State Minimisation, Optimisation and Timing. Hardware Description Languages (VHDL)  Combinatorial descriptions  Delta Delays  VHDL hierarchy (Entities, modules, instantiation)  Language constructs (conditional assignment, selected assignment)  Synchronous descriptions (processes, if, case)  VHDL test benches  Synthesis considerations

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    Explain and help understand Ethernet MAC/PHY RTL from github. Required: - Industry experience in digital/mixed-analog IP RTL design, preferably Ethernet IP. Meetings will be conducted via zoom/meets. Thank you!

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    Verilog program to fpga 已经结束 left

    Program on vivado (verilog), morse code. Binary for "BASYS 3" fpga, simulation, files...etc More details via chat

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    I need to implement an Ed25519 Algorithm in Verilog for FPGA implementation that can properly simulate on Xilinx Vivado Design Suite. The complete algorithm code is already available in C language and I want to convert it into Verilog. Link:

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    Given any Verilog netlist of a digital circuit in gate-level format, the code should extract critical path. Critical path is the longest path from input to output port. There could be multiple inputs/outputs in a given circuits. Critical path can be the longest path from any input to any output based on the connections in the circuit.

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    I need a vhdl master to code a RISC processor with multiple components. I will give the detailed information.

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    need to make truth table and Circuitry Design and verilog code and testbench for fibonacci series generator

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    FPGA Developer 已经结束 left

    I have rich experience with FPGA I developed FPGA based IDS(Intrusion Detection System) I am strong at C, C++, Verilog and son on

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    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C , C++

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    Help with VHDL 已经结束 left

    I have to implement a pipelined DLX processor. I have already constructed the single staged processor. However, I will need you to do the pipelining part which would include the pipelined control, and relevant harard detectors, forwarding unit, and bypassing mechanisms. The project now has been implemented using a supermodular approach where I have tried to make the VHDL codes for the smallest units and then built them upwards in the schematic. I will need the schematic of the pipelined dlx too. here is the drive link with all the files for your reference I have a certain benchmark to run which i will share once i get to design it but the i will need the isim simulations of the entire processor as a proof that

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    hi there i need an electrical or electronics engineer who is expert in VHDL AND RISC-V for simple task more details will be shared with the suitable candidates in the inbox regards

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    VHDL and risc-v LAB work 已经结束 left

    hi there i need an electrical or electronics engineer who is expert in VHDL AND RISC-V for simple task more details will be shared with the suitable candidates in the inbox regards

    $235 - $1959
    加封
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    hello, please contact me if you are proficient in the fields above

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    Assalam o alaikum !!! We are looking for electrical engineers to join our team and work on different projects related to following domains of electrical engineering: 1) Control System 2) Satellite communicati...related to following domains of electrical engineering: 1) Control System 2) Satellite communication 3) Radio frequency and microwave circuit design 4) VLSI techniques 5) Radar theory and satellite communication 6) Intelligent and adaptive systems 7) Digital design 8) Asic design Freelancers must be proficient in following: 1) Matlab / Simulink 2) Proteus 3) Multisim 4) pspice 5) LTspice 6) VHDL/Verilog coding What I am expecting: 1. Dedication to the work 2. On time delivery of work without any delay 3. Well arranged and properly formatted reports with plagiaris...

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    We are looking for electrical and electronics engineers with good experience in following areas: • Embedded C Programming. • VHDL/Verilog, LabVIEW/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. Feel free to place your bid and mention your areas of expertise in your proposal. we highly encourage new freelancers to apply for this post.

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    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C , C++

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    Labwork assistance 已经结束 left

    I have a few labs im struggling with and they all follow one another. It requires VHDL, RARS and Ripes. Please contact me so I can show you the details and so we can get started on this. Thanks!

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    Fpga project 已经结束 left

    1. "idle" state: It is the state when the machine is doing nothing and is idle. In "idle" state, if power button is "on" then the state transition takes place from state "idle" to state "a" and the output is low. If power button is "off ", then the state remains in "idle". 2. "a" state: In state "a", if fill_water is 1(tha...state of the machine. In "c" state, if the water is filled that is if fill_water = 1, then the process gets completed and the state returns back to its idle state and the output is 1. Otherwise it remains in state "c". and in state a it depends on weight for example : 0-2 kilo 3 seconds to fill water 3-5 kilos 5 seconds 6-7 kilos 8 seconds for the weight 3bit...

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    Integrated circuit design 已经结束 left

    Verilog/VhDL FPGA Asic Electronics Microcontroller

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    Hey I need someone who knows how to deal with integrated circuit design and vhdl

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    Hi, just to make sure. Do you have the Nexys 4 DDR board and vivado 2020.1 installed? Also, Do you have knowledge of multithreaded OS, in particular FreeRTOS? detail will be share in chat box

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    The instruction set for the processor RISC-V should be expanded. Hardware implementation of RISC-V processor with pipeline is already done (There is 5 stages of pipeline: Fetch, Decode, Execute, Memory and WriteBack). VHDL files are in attachment. The task is to upgrade this processor with 20 new instructions. For each instructions there is possibility of appearance of the hazard. Every hazard must be resolved. In the documentation there is explanation for the hazards as well as their elimination. Also, in VHDL files, there is implementation of blocks which remove hazards. Just ADD, AND, SUB and OR instructions are implemented in RISC-V. Current implementation of RISC-V support just this 5 instructions, so update of RISC-V is need it for 20+ new instructions For interactive ...

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    Hi, just to make sure. Do you have the Nexys 4 DDR board and vivado 2020.1 installed? Also, Do you have knowledge of multithreaded OS, in particular FreeRTOS?

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    design a single cycle mips proccessor computer Architecture vhdl

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