...logical functions with status outputs ready for branching logic • Register File with dual-read / single-write ports, parameterisable depth, and a simple hazard-free write-back mechanism • Instruction Decoder that converts the Alpha binary format into the internal control signal set expected by the software controller Multiplexer and control unit I’m happy for you to implement the blocks in Verilog, VHDL, or SystemVerilog—choose whichever fits your workflow—as long as the modules synthesize cleanly in a mainstream FPGA toolchain and come with a self-checking testbench. Deliverables will be: 1. Source code for each module, clearly commented 2. A top-level wrapper that shows how the software control path interacts with the datapath signals...
I need...layout, register map, datapath diagrams, and a worked example for each arithmetic instruction • Verilog-style pseudocode snippets highlighting the control logic for each stage • Timing diagrams illustrating memory latency tolerance and stall behaviour • A short validation checklist I can run against my RTL to confirm correct arithmetic/memory interaction Acceptance Criteria All arithmetic instructions must be explained down to cycle-accurate behaviour, with no gaps between the execute stage and main-memory write-back. Diagrams and code should compile or render without edits. Tools and references such as Alpha Architecture Reference Manual citations, WaveDrom for timing visuals, or Verilog pseudocode are welcome—use whatever communicates ...
...end goal. What I need built: A Verilog module that controls laser pulse timing, reads x/y/z sensor coordinates, calculates next plasma position, and drives galvo mirror signals — all within a tight real-time feedback loop. Simulation in Xilinx Vivado first, then synthesis onto FPGA hardware. You need to know: Verilog / VHDL FPGA development (Xilinx preferred) Real-time control systems Basic understanding of laser or optics systems is a plus Deliverables: Vivado project with full simulation testbench Timing verified under 10 microseconds end-to-end Clean documented code ready for hardware synthesis This is a serious research project with long-term scope. Looking for someone sharp who understands real-time hardware constraints, not just someone who writes ...
...end goal. What I need built: A Verilog module that controls laser pulse timing, reads x/y/z sensor coordinates, calculates next plasma position, and drives galvo mirror signals — all within a tight real-time feedback loop. Simulation in Xilinx Vivado first, then synthesis onto FPGA hardware. You need to know: Verilog / VHDL FPGA development (Xilinx preferred) Real-time control systems Basic understanding of laser or optics systems is a plus Deliverables: Vivado project with full simulation testbench Timing verified under 10 microseconds end-to-end Clean documented code ready for hardware synthesis This is a serious research project with long-term scope. Looking for someone sharp who understands real-time hardware constraints, not just someone who writes ...
I’m working on an FPGA-based power-electronics design that performs direct AC-to-AC conversion, and I’d like an experienced set of eyes on the project. Rather than a full redesign, I need targeted, practical suggestions that will help refine the existing architecture, tighten the control loops, and ensure the hardware description (VHDL/Verilog) and gate-level timing are truly aligned with the switching requirements of high-frequency power conversion. Here’s what I’m looking for: • A concise design review of the current top-level schematic, clocking scheme, and PWM generation logic. • Specific, actionable recommendations for improving efficiency, reducing switching losses, and safeguarding against common AC-to-AC pitfalls such as commuta...
...ENCLUSTRA module that is now out of production; a newer ENCLUSTRA board has already been chosen and I need the current HDL project moved over so it runs flawlessly on this hardware. The focus is strict functional compatibility: the migrated bitstream must interface with the same peripherals, respect the same I/O timing, and deliver identical behaviour to the legacy product. The codebase (mixed VHDL/Verilog with some Xilinx IP cores, other) already builds under Vivado, and I can provide constraint files, limited board documentation, and schematics for the new module. You will analyse the differences, update pin-outs, clocks, memory interfaces, and any IP parameters affected by the hardware change, then verify the design through simulation and an on-board test build. D...
I already have both xschem and KLayout running, using the GF180MCU library. I entered an xschem schem...both xschem and KLayout running, using the GF180MCU library. I entered an xschem schematic of a small logic block, and a gds after placement and routing. I am able to pass klayout DRC, but not LVS. Here is what I need: • fix my xschem symbols for about 6 logic cells to support writing out a verilog netlist for logic simulation, and a spice netlist for LVS. • I want the verilog netlist to include simple risedel and falldel for the gate-level simulation • I want the spice netlist (and NOT the verilog netlist) to include power and ground global connections so LVS can pass in klayout. I can provide my design data for you to clean up and show it run...
...custom boards that combine an FPGA-based signal generator with several ESP32 modules. The immediate gap is in analog and digital circuit design: I need a fresh set of eyes to review, debug, and improve the front-end and conditioning stages so our multi-channel waveforms stay clean from kHz up into the low-MHz range. You will also find yourself touching the programmable logic; I use both VHDL and Verilog, so fluency in either (or ideally both) is welcome when tweaks to the signal-generation core are required. On the microcontroller side each ESP32 handles data processing, manages communication protocols, and drives attached peripherals, all written in C/C++. Expect to dive into that firmware whenever hardware changes ripple upward. Key objectives • Analyse and ...
...bus activity. Solid knowledge of USB/PCIe link training, BAR mapping, and DMA engines is essential. The host application should be written in modern C++ or C#; it will initiate read/write calls, parse common game data structures, and integrate stealth measures against EAC, BattlEye, and Vanguard without interfering with legitimate system processes. Deliverables • FPGA bitstream + source (Verilog/VHDL) • Windows 10/11 host executable with full C++/C# source • Well-commented code and build scripts • Developer documentation that walks through setup, firmware flashing, API usage, and anti-cheat mitigation tactics • A short demo that captures player coordinates and health from a current FPS title to prove reliability and throughput Acceptanc...
...my bench, and guide me from concept through verified implementation. The immediate need is flexible: you might end up drafting fresh schematics for a small FPGA-based subsystem, debugging timing faults in an existing logic chain, or simply showing me how to streamline test-bench simulations so I can spot issues earlier in the cycle. Your familiarity with tools such as MATLAB, LabVIEW, or VHDL/Verilog will be invaluable—feel free to lean on whichever environment you know best as long as it gets us to reliable, reproducible results. I’ll share all current documentation, measurement data, and constraints as soon as we connect so you can propose a clear plan of attack. Deliverables will include: • Verified logic design or fix, shared as source files and a...
For my current project I need a custom logic circuit created and fully verified inside Intel Quartus Prime. Once the job begins I’ll forward the truth table and timing requirements; from there, the work involves writing the VHDL or Verilog, setting up the Quartus project and pin constraints, compiling to a clean build, and running a simulation to prove the behaviour. Deliverables • Complete Quartus Prime project folder (.qpf, .qsf, source, constraints) • Generated bitstream (.sof) and simulation waveforms • Brief README outlining build steps, clocking and any device-specific notes Acceptance criteria – Project opens and compiles without critical warnings – Testbench passes all functional cases provided – Bitstream operate...
I need a CPM GMSK demodulator implemented in VHDL for a signal processing system. Targeting data rates of 8 Mbps with system clock of ~100 MHz Key Requirements: - VHDL expertise - Experience with CPM and GMSK modulation/demodulation - Background in signal processing Ideal Skills: - Ability to meet high bit rate requirements - Knowledge of hardware integration Please provide relevant experience and approach.
I'm seeking an experienced FPGA developer who can assist with design and development, specifically in HDL coding, using both VHDL and Verilog. Ideal Skills and Experience: - Proficiency in both VHDL and Verilog - Strong background in FPGA architecture - Experience in integrating and interfacing FPGAs with other systems - Ability to test, debug, and optimize designs Please provide relevant project experience and a brief portfolio. Looking forward to your bids!
I need an experienced FPGA programmer to assist with a data processing application. Key Requirements: - Proficiency in at least one of the following FPGAs: Xilinx, Altera, Lattice - Expertise in data processing applications - Familiarity with VHDL, Verilog, or SystemVerilog Ideal Skills and Experience: - Proven track record in FPGA programming - Strong background in data processing algorithms - Ability to work with various FPGAs and HDLs Please provide relevant experience in your bids. We need to develop ethernet hub in fiber optic 2 ports , and 16 SPI for chip led controller using data and clock . SPecia Ethernet protocol defined by us.
...are building a hardware-accelerated probabilistic engine that runs QUBO/Ising workloads for Logistics, Finance, and Cyber-Intelligence, and I’m open to engaging specialists across several tracks: • ML Engineer – craft graph neural networks and matrix-compression pipelines that translate complex optimisation problems into sparse, hardware-friendly representations. • FPGA Engineer – write VHDL/Verilog kernels for AWS F1, pushing the solver to micro-second latency. • Backend Architect – design a high-performance API layer in Go, Rust or Python that orchestrates FPGA instances, manages job queues and exposes REST/gRPC endpoints. • Cyber-Security Expert – conduct cryptanalysis and network-intelligence research to harden...
I am building a Verilog-based, real-time Sobel edge detector that streams video from an OV7670 camera to a monitor over VGA on a Nexys A7-100T board, all within Xilinx Vivado. The architectural concept is clear, yet the project’s success now depends on rigorous simulation, validation, and concise documentation suitable for an academic submission. Your main focus will be designing an efficient test and simulation strategy: self-checking test-benches, frame-level functional coverage, timing verification, and any other diagnostics that prove the design meets real-time performance. I am open to whichever simulation environment you consider best—whether you stay inside Vivado’s integrated simulator or introduce ModelSim, Verilator, or another workflow—provided it...
...implement multiplexers and demultiplexers. The goal is to move from logic-level concepts all the way to a working circuit that can be demonstrated in the lab. Here is what I’d like from you: • A clear derivation of the truth tables, Boolean expressions, and any Karnaugh-map (or equivalent) minimisation that leads to the final gate-level schematic. • An HDL version of the same circuit (Verilog or VHDL—whichever you prefer) that compiles cleanly and is ready for simulation. • Simulation results that verify correct operation for every input combination; ModelSim, Vivado, Quartus, or Logisim waveforms are all acceptable. • Brief, well-commented documentation so I can present the design during our tutorial session and explain each decisio...
I need a synthesizable, timing-clean Verilog implementation of the classic MUSIC (Multiple Signal Classification) algorithm that can estimate the direction of arrival of one or more narrow-band signals received on a uniform linear array of four antennas. The end use is a radar front-end, so accuracy takes priority over latency or power. Scope • Design the fixed-point signal-processing chain on an FPGA (I am currently working with Xilinx Series parts; feel free to suggest an equivalent if it helps meet timing). • Implement covariance matrix formation, eigen decomposition and the pseudospectrum peak search entirely in hardware; no soft-core processors or external DSP chips. • Include provisions for array calibration coefficients so the design can be tuned on-si...
I need clean, well-documented VHDL that implements a set of simple digital circuits on an FPGA. The task sits firmly in the Digital circuits design space—no signal-processing tricks or embedded firmware layers—just straightforward gate-level logic and a few flip-flops brought to life in hardware. Here is what I expect: • VHDL source files for each module • A small, self-checking testbench that runs in ModelSim/Questa or an equivalent simulator • Clear synthesis-ready code that fits easily onto a mid-range Xilinx or Intel development board (the exact board can be generic; resources should stay minimal) • A short README outlining how to simulate, synthesize, and pin-map the design Because the scope is intentionally simple, I value concis...
...verification. • Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues. • Work on functional & code coverage verification. • Provide technical support to other teams PREFERRED EXPERIENCE: • Experience with C/C++ • Experience with Verilog, System Verilog, and modern verification libraries like UVM • 6years of ASIC design verification experience • Experience / Background with DDR or Memory Controller. PHY Verification is a plus • Experience with scripting languages like Python, Perl and TCL is a plus. • Collaborate with architects, hardware...
...verification. • Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues. • Work on functional & code coverage verification. • Provide technical support to other teams PREFERRED EXPERIENCE: • Experience with C/C++ • Experience with Verilog, System Verilog, and modern verification libraries like UVM • 6years of ASIC design verification experience • Experience / Background with DDR or Memory Controller. PHY Verification is a plus • Experience with scripting languages like Python, Perl and TCL is a plus. • Collaborate with architects, hardware...
I'm seeking an experienced FPGA developer to help debug logical errors in existing VHDL code for a Lattice Semiconductor MachX03 development board. Key Requirements: - Expertise in VHDL - Experience with Lattice Semiconductor FPGAs - Strong debugging skills, especially with logical errors Ideal Skills and Experience: - Proven track record in FPGA development and debugging - Familiarity with MachX03 specific features and tools - Ability to provide clear, concise solutions and documentation Looking forward to your expertise!
...production contract covering up to 8,000 diagrams, with further scale potential. Project Overview The objective is to collect and deliver technical diagram images representing electrical and digital design concepts, paired with either: Verilog HDL code, or Clear, structured technical explanations in English These assets will be used in advanced AI/ML and engineering research applications. Dataset Requirements Each diagram must conform to one of the following variants: Variant 1 Original technical diagram image Corresponding Verilog Hardware Description Language (HDL) code Variant 2 Original technical diagram image Detailed English technical description explaining the circuit’s function and behavior All diagrams must be original and bui...
I have already begun converting the VHDL Language Reference Manual—about 700 pages—from its original PDF to LaTeX, but only scattered portions are finished. Roughly the first nine sections of the thirty-four total have a draft translation; the rest is still untouched or only partially copied over. All existing .tex sources, my compile script, and the official style guidelines (custom class file, macro set, and layout notes) will be in the hand-off package so you can follow the exact formatting rules that match the published standard. Figures, tables, and cross-references must render cleanly under pdflatex without manual post-processing. What I need from you is the full, consistent LaTeX source that: • covers every remaining section and appendix, completing the 70...
...tied to tape-out milestones. Your compensation is therefore predictable and performance-linked rather than speculative. Roles we still need to fill (4+ yrs exp each) System architects, embedded and systems programmers, verification engineers, physical design specialists, DevOps for CI/CD of RTL builds, HR lead for technical hiring, tech managers and team leads. Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected. What to include in your application Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring;...
...tied to tape-out milestones. Your compensation is therefore predictable and performance-linked rather than speculative. Roles we still need to fill (4+ yrs exp each) System architects, embedded and systems programmers, verification engineers, physical design specialists, DevOps for CI/CD of RTL builds, HR lead for technical hiring, tech managers and team leads. Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected. What to include in your application Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring;...
...multi-disciplinary expert or a small team to assist in a high-fidelity hardware research project focused on PCIe device emulation and DMA-based memory forensics. The goal is to develop a custom FPGA-based solution that can perfectly mimic a legitimate consumer PCIe device (e.g., Network or Storage Controller) to pass low-level system integrity checks. Key Responsibilities: Emulation (FPGA/Verilog): Develop custom firmware for an Artix-7/35T/75T FPGA board to emulate a real-world donor device's configuration space and TLP behavior. Development (C/C++): Create a high-performance Windows/Linux driver for direct memory access via the PCIe bus, ensuring stability and low latency. Analysis: Design a system to read and analyze specific application memory segments in real-time
I need a digital-only control circuit taken from concept through a production-ready schematic. The task sits firmly in the circuit-design branch of electrical engineering: no analog front-end...straight to PCB layout later. • Provide accompanying design files: schematics, netlist, component libraries, and a concise design-rules document. • Run basic simulations or logic-timing checks to verify that the circuit meets the specified control timings before hand-off. Everything should stay purely digital; no mixed-signal blocks are expected at this stage. If you are comfortable with Verilog/VHDL for behavioural validation, that is a plus but not mandatory—the key deliverable is a schematic ready for layout and prototyping. Let me know your favourite toolchain ...
I need a digital-only control circuit taken from concept through a production-ready schematic. The task sits firmly in the circuit-design branch of electrical engineering: no analog front-end...straight to PCB layout later. • Provide accompanying design files: schematics, netlist, component libraries, and a concise design-rules document. • Run basic simulations or logic-timing checks to verify that the circuit meets the specified control timings before hand-off. Everything should stay purely digital; no mixed-signal blocks are expected at this stage. If you are comfortable with Verilog/VHDL for behavioural validation, that is a plus but not mandatory—the key deliverable is a schematic ready for layout and prototyping. Let me know your favourite toolchain ...
I’m looking for an experienced Digital VLSI / ASIC engineer to complete a small end-to-end RTL-to-power analysis project using Cadence tools. The project follows a standard ASIC front-end flow: RTL design → synthesis → gate-level simulation → power estimation. All project structure, templates, and documentation are provided.
I’m looking for an experienced Digital VLSI / ASIC engineer to complete a small end-to-end RTL-to-power analysis project using Cadence tools. The project follows a standard ASIC front-end flow: RTL design → synthesis → gate-level simulation → power estimation. All project structure, templates, and documentation are provided.
I’m looking for an experienced Digital VLSI / ASIC engineer to complete a small end-to-end RTL-to-power analysis project using Cadence tools. The project follows a standard ASIC front-end flow: RTL design → synthesis → gate-level simulation → power estimation. All project structure, templates, and documentation are provided.
will share info in chat. only professional worker
I need a complete RTL design in Vivado that produces an up-chirp based on a sinusoidal input and sweeps from 50 MHz up to 55 MHz. Once generated, this signal must feed directly into an 8192-point FFT, so I can observe the dominant frequency bins in hardware. The core tasks are: • Write synthesizable VHDL / Verilog for the chirp oscillator, parameterised for the 50–55 MHz sweep. • Instantiate and configure the Xilinx FFT IP for 8192 points, wire it to the chirp stream, and handle any required data-format conversions or hand-shaking. • Provide timing-compatible top level, constraints, and a self-checking test-bench that sweeps the chirp, captures the FFT output, flags the peak bins and dominant frequencies. Acceptance is straightforward: when I run t...
...HDMI transmitter. I need a complete Vivado project that captures 1080p video from both ADV7611 receivers, performs basic in-FPGA signal processing (frame buffering, colorspace conversion or simple image filter—whichever is cleanest to showcase the path), and then drives the SiI9134 so the processed stream displays correctly on an external monitor. The project must be written in synthesizable Verilog or VHDL, use the latest Vivado tool-flow, and include: • Top-level RTL connecting the ADV7611 I²C, video, and clock lines to the SiI9134 interface on the XC7A200T • A timing-clean 148.5 MHz pixel clock domain plus any required gearboxes or FIFOs for 1080p@60 Hz • Minimal but working video-processing block(s) showing real-time manipulation (e.g., ...
I'm seeking an experienced developer to design an application-specific vector processor, primarily for scientific computing. This processor will be targeted for embedded systems and should be developed using Verilog or VHDL. Key Requirements: - Design and implement a vector processor architecture. - Optimize the processor for scientific computing tasks. - Ensure compatibility and efficiency on embedded systems. - Develop in Verilog or VHDL. Ideal Skills and Experience: - Strong background in digital design and hardware description languages (Verilog/VHDL). - Experience with embedded systems and scientific computing applications. - Ability to optimize hardware for specific workloads. Please provide a portfolio showcasing similar projects and...
I am looking for an experienced FPGA developer to write functional Verilog code for interfacing a 1-wire secure EEPROM with a Zynq Zed Board. The EEPROM includes SHA-1 authentication. The deliverables should include: - Fully functional Verilog code for the interface. - Proper handling of SHA-1 authentication. - Compatibility with the Zynq Zed Board.
I have already drafted a Smart Parking Gate Controller and will share the exact list of inputs, outputs, and the eight required operations as soon as we start. What I need now is the complete digital logic implementation: • Build the full truth table from my specifications. • Derive simplified Boolean expressions (K...outputs, and the eight required operations as soon as we start. What I need now is the complete digital logic implementation: • Build the full truth table from my specifications. • Derive simplified Boolean expressions (K-map or equivalent). • Draw a clean logic-gate schematic. • Produce a working simulation in Logisim and deliver matching VHDL code so I can integrate it later. Other tasks: 1-study state 2-truth table 3-K-maps 4-log...
Design and implement a basic 8 Bit CPU on an FPGA board The implementation will use Verilog (or VHDL if preferred) and target a standard, widely available FPGA board like the Xilinx Coartex-A7 ensuring compatibility with Vivado. Deliverables • HDL source: well-commented modules for datapath, ALU, control unit, registers, and memory interface • Testbenches: simulation covering each instruction, plus a self-checking program counter/ALU regression • Vivado artefacts: implemented design, timing summary, resource utilisation report • Schematics: readable datapath and control diagrams (PDF or PNG) • Documentation: 4–6-page write-up describing micro-architecture choices and verification plan • Bitstream + demo program: ready-to-flash ...
... get the controller blocks synthesised, and prove they behave identically once they’re running on silicon. Sensor integration and data logging can wait; the immediate focus is control-algorithm work and, in particular, thorough algorithm testing after it lands on the chip. Deliverables • Partitioned Simulink model with the guidance/control section prepared for HDL Coder • Synthesizable VHDL/Verilog project targeted to the DE2-115 and built in Quartus • Configured Simulink FIL interface (JTAG link, board files, timing setup) • Automated test bench in Simulink that compares host versus FPGA outputs and confirms fixed-point accuracy • Short, clear setup guide so I can reproduce every step on my own machine Acceptance criteria The c...
Assalam o alaikum, I am lo...simulation and report writing with zero plagiarism. (use of chatGPT highly prohibited). I am looking for experts who can deal FYP related to following domains of electrical engineering: Power Systems / Renewable energy systems Control Systems Signal Processing Instrumentation Engineering Internet of things Freelancers must be proficient with following: • Arduino/Raspberry Pi • FPGA | Verilog/VHDL • Proteus | TinkerCAD • Multisim | LabVIEW • MATLAB/SIMULINK & Python ***MOST IMPORTANT*** Applicants should be proficient in technical report writing and must have good command over proper formatting of final year reports by following their templates provided by different universities. Reports shoul...
...storytelling. The Role: We’re seeking a full-time direct report who is both a skilled FPGA developer and a creative marketer. You’ll be responsible for building FPGA learning content, engaging our community, and driving growth across multiple digital channels. Core Responsibilities: - FPGA Development & Content Creation (blogs, technical articles, demo projects) - Hands-on Verilog design (other HDLs like VHDL, SystemVerilog a bonus) - Create FPGA learning blogs, tutorials, and educational resources - Develop demo projects and showcase them in accessible formats Digital Marketing & Community Engagement - Run newsletters and manage a content calendar - Write clear, engaging technical articles in excellent English - Manage so...
I’m pushing a fast-turnaround project and need another pair of expert hands. The goal is a small, custom CPU core—built purely in Verilog or VHDL—tuned for signal-processing tasks and proven on a Xilinx board you already have running on your bench. I’ll supply the high-level instruction set, throughput targets, and the specific signal operations I need accelerated. You’ll translate that into a synthesizable design, simulate it, meet timing, and show it running on your board so we can iterate in real time. Deliverables • RTL source (Verilog or VHDL) • Simulation test-bench with passing waveforms • Synthesized design for a recent Xilinx family (Vivado project or equivalent) • Resource and timing repor...
Note: The project must include code, schematics, and a short technical write‑up. ● Design a basic CPU (even 8‑bit or a minimal RISC‑V subset) in Verilog/VHDL, implement it on a low‑cost FPGA board, and run a small instruction set or demo program, emphasizing microarchitecture choices and timing closure. ● Deliverables: HDL source, timing/area reports, simulation testbenches, and a brief report on design methodology and verification strategy. ● Mixed‑signal sensor acquisition front‑end Note: The project must include code, schematics, and a short technical write‑up.
Aqui está uma sugestão de descrição de projeto, otimizada para publicação em uma plataforma como a Freelancer.com, com base no documento que você forneceu. Título da Vaga Projetista VHDL/Verilog para Processador MIPS 32-bits (Pipeline e Cache) Descrição Completa do Projeto Estou buscando um desenvolvedor experiente em VHDL ou Verilog para completar um projeto acadêmico de arquitetura de computadores. O projeto é dividido em duas partes principais, e o freelancer deve entregar ambas as partes para a conclusão do trabalho. O objetivo é projetar e implementar um processador MIPS de 32 bits, começando com um design básico e, em seguida, evoluindo-o para u...
I need a VHDL IP core that sits between two AXI4-Stream FIFOs, ingests a packet of N values, performs a simple arithmetic tweak, and pushes the result back out. Here is the exact scope: • Interface: one AXI4-Stream slave for input, one AXI4-Stream master for output. • Packet size: parameterised (e.g. default 8 words, 32-bit each). • Operation: addition with a constant, hard-coded inside the source (no run-time configuration needed). • Overflow handling: if more than N words arrive before TLAST, raise a dedicated error line and discard the surplus. • Deliverables: – Readable, synthesizable VHDL source for the core. – A self-checking test-bench (ModelSim/Questa or similar) that drives typical and corner-case traffic, shows t...
...constraints file (SDC) handling clock, IO delays, and false/multicycle pathsPower planning and optimization for low power operation (optional if applicable)Final GDSII or layout database for tapeout or further place-and-route stepsTiming reports demonstrating timing closure with specified constraintsVerification of design correctness via post-layout simulation support files (optional)Provided Files:RTL Verilog sources for SPI, I2C, UART modules, and the top-level Multi-Protocol Conversion Unit (mpcu_all.v and associated testbenches)Protocol conversion logic (conv_protocl.v)Research and design analysis paper ("")Sample SDC constraints file (can be enhanced/modified as per target technology)Constraints and Environment:Clock frequency:
I’m planning an automotive-grade ASIC focused on reliable sensor interfacing and need a seasoned embedded engineer to shape the initial blueprint. Here’s what I’m looking for: • A high-level architecture that defines power domains, I/O pinout, and core logic blocks dedicated to sensor data acquisition. • Block-level Verilog or VHDL stubs for the key sensor interface modules so I can validate feasibility on my end. • Basic timing, power, and temperature estimates suitable for an automotive environment (-40 °C to 125 °C). • A short BOM or technology recommendation—foundry node, package type, and any external components essential for stable operation. Keep the scope to this early concept stage; I’m not seeki...
I need a Verilog implementation of a CNN accelerator with a DRAM interface. The accelerator should perform matrix multiplication on fixed-size matrices. The DRAM interface should be DDR3. Key requirements: - Functionality: Matrix multiplication only - Matrix type: Fixed-size matrices - DRAM interface: DDR3 Ideal skills and experience: - Proficiency in Verilog - Experience designing CNN accelerators - Knowledge of DRAM interfaces, specifically DDR3 - Strong background in digital design and hardware description languages Please provide relevant experience in your bids.
