You are requested to suggest and develop a hardware solution to correcting the IQ phase error in QPSK transmission and demonstrate your solution in VHDL. In particular, present an analysis of the precision requirements for the data used in within the VHDL code and an analysis for clock speed requirements assuming typical data sampling frequencies. might provide some overview information in QPSK system. Do not hesitate to ask me if you have anything unclear. Many thanks Martin ## Deliverables Most importantly description of error correction algorithm, Then, in case there is time left, VHDL code, some screen shots of simulation, implementation details/description. ## Platform Any Windows server, XP or Vista
We are asked to do the following: 1. Develop a VHDL model of a complete QPSK system, as specified in Section 4.1 in , and implement it on a suitable Xilinx or Altera FPGA. 2. Develop and implement a VHDL module and a suitable PC application to send the IQ phase errors to a PC over a USB link and display the errors on the PC screen. 3. Suggest and develop a hardware solution to correcting the IQ phase error and demonstrate your solution in VHDL. In particular, present an analysis of the precision requirements for the data used in within the VHDL code and an analysis for clock speed requirements assuming typical data sampling frequencies. 4. In addition to the technical work specified above, write a chapter in your report on methods, ethics and responsibilitie...
Hi, I need to develop HDL editor with a) Verilog(HDL) syntax correction, b) with dynamic hints for good coding guidelines (as and when designer writes code, gets hints by editor for good coding rules). c) along with above functionality I need to have basic editor functionality like marking, copying, pasting, folding of code, etc. Also editor should be MDI application and should be platform independent (Mostly editor will be run on linux system and X windows). (I shall provide detailed RS (Requirement Specification) once developer is decided) For above editor I need developer who can develop it using wxWidgets (scintilla lib ). wxWidgets has already developed libraries for editor functionality. Hence one only has to use them and just add wrapper of rules
Hi, I need to develop HDL editor with a) Verilog(HDL) syntax correction, b) with dynamic hints for good coding guidelines (as and when designer writes code, gets hints by editor for good coding rules). c) along with above functionality I need to have basic editor functionality like marking, copying, pasting, folding of code, etc. Also editor should be MDI application and should be platform independent (Mostly editor will be run on linux system and X windows). (I shall provide detailed RS (Requirement Specification) once developer is decided) For above editor I need developer who can develop it using wxWidgets (scintilla lib ). wxWidgets has already developed libraries for editor functionality. Hence one only has to use them and just add wrapper of rules
...the E12MUX architecture and model the E12MUX in Verilog. The FPGA being targeted should be considered and synthesizable code should be written targeting the efficient usage of chosen FPGA resources. The model should be simulated in any industry standard simulator Perform the following and report the same in your assignment: 1. Identify the sub blocks for the selected architecture of E12MUX 2. Model the design using verilog HDL, carry out the functional simulation and verify the results with appropriate input test cases. 3. Simulation and analysis of results obtained using multiple test cases to prove E12MUX Problem Statement: Part B 1.) For the E12MUX designed in part A above write an efficient test bench in Verilog 2.) The test b...
I want to write a code in verilog to make a cryptographic coprocessor for smartcards. I dont have the architecture of it. If anyone have the architecture that will be a great help. If anyone can give code along with the architecture and the details of it that will be superb. The coprocessor use RSA algorithm for security.
Implement a virtual CPU in C and write a backend for the latest stable version of the Portable C Compiler ( ) for it. ## Deliverables I want to develop a novell CPU core for a FPGA in VHDL. For this CPU I need a C compiler. Your task is the following: - get the latest stable version of the Portable C Compiler (PCC) from - analyze, how the backend code generation works - propose a simple instruction set for a CPU, which can map the intermediate representation of PCC very direct to the instruction set and document in detail how this mapping can be done. Floating point support is not required, only a very basic register machine, which can be used for implementing the compiler backend, for compiling simple C programs for embedded systems
**Add to an existing FPGA project two new functionality.** Programming environment: Xilinx ISE 11.2 Xilinx device: XC3S700AN Simulator is required to check design Phase angle: Calculate the angle between three analogue signals of a three phase power system namely phase 1, 2 and 3. The code for sampling the signals are already implemented. The signal need to be filtered...is available and a 10Mhz clock is available at two I/O pin of the FPGA. A 24 bit counter (GPS counter) will be incorporated into the FPGA, clocked by the 10 MHz clock and reset by the PPS. When the phase voltages crosses zero, the content of the GPS counter is transfer into a corresponding register to be transfer to a microcontroler. ## Deliverables The programming language must be ...
Pipeline Datapath VHDL. build a structural model of the pipelined datapath in VHDL from behavioral components such that Hazard Detection and Forwarding Units and the Pipeline Registers as well as some reused components from single cycle version of the datapath.
...pl/rtvforum/ Całość polega na wpisywaniu propozycji nowych tematów w specjalnym polu tekstowym pod danym tematem. Krok 1. Wyświetlamy listę tematów Krok 2. Przechodzimy do wybranej dyskusji, zapoznajemy się z treścią pierwszej lub/i kolejnych wiadomości. Krok 3. Wpisujemy propozycje tematu poniżej tytułu wiadomości, klikamy przycisk wyślij. Przykład, temat: VHDL, powinien być VHDL co to jest i do czego służy? AF 0300 powinien być: Poszukuję aplikacji układu SAF 0300, w sterowaniu tachografu Windows XP i Neostrada powinien być: Windows XP i Neostrada, problem z szybkością neostrady Prezentacja: Praca bardzo prosta, ale wymagająca szybkiego czytania, analizowania i pisania, najlepiej widziana osoba z wykształceniem
LOCO-I is an implemantation of jpeg-ls from HP. Attached is a report of the ITU-T algorith Also there are some open source implementations e.g. the one attached This job requires the implementation in VHDL of the circuit of the encoder. and the comparison of the VHDL made encoder to other open source encoders - implemented in c or other language in terms of performance. I will require the implementation as well as the documentation I need someone expert willing to be communicate as well
The goal of this project is to optimize VHDL logic that is currently using 107 macrocells in a Xilinx CPLD to 72 macrocells so it can fit in a smaller component. The logic implements an SPI slave and a simple bus controller. Optimized logic should build with Xilinx Webpack ISE 11.x. More specifications available to potential contractors. Please state your previous VHDL experience.
Experience Requirement: Experience understanding source co...sufficient to be able to review and locate key code segments within source code. Travel Requirements: Travel to a secure facility in the United States to review source code will be required. Reasonable travel costs will be reimbursed in addition to the project costs. Project: Engineer to review source code, including assembly language code and possibly higher level block diagrams and VHDL documents related to cell phone chipsets such as Intel PXA, TI OMAP chips and Qualcom MSM chips in order to determine the specific algorithms being deployed for particular procedures. Other Requirements: You will be required to execute a protective order and other agreements promising to keep the information you review con...
: Web application to create VHDL & Verilog test benches Hotbench () is allow-cost test bench generation web-application. It helps engineers to intuitively create test bench with by using mouse clicks. The application is fast and support both VHDL and Verilog HDLs for generating test bench. Web-based application makes the tool unique in overcoming geographical boundaries and OS (platform) independence. User management/GUI and login IDs for user ensures security. The web application allows HDL users to login and select for HDL options from VHDL/Verilog. And then enter the entity/module declaration that contains IO ports for their Unit Under Test (UUT). The users then select for best patterns in order to test & verify their design...
Hi, I need to develop HDL editor with a) Verilog(HDL) syntax correction, b) with dynamic hints for good coding guidelines (as and when designer writes code, gets hints by editor for good coding rules). c) along with above functionality I need to have basic editor functionality like marking, copying, pasting, folding of code, etc. Also editor should be MDI application and should be platform independent (Mostly editor will be run on linux system and X windows). (I shall provide detailed RS (Requirement Specification) once developer is decided) For above editor I need developer who can develop it using wxWidgets (scintilla lib ). wxWidgets has already developed libraries for editor functionality. Hence one only has to use them and just add wrapper of rules
Hi, I need to develop HDL editor with a) Verilog/VHDL syntax correction, b) with dynamic hints for good coding guidelines (as and when designer writes code, gets hints by editor for good coding rules). c) along with above functionality I need to have basic editor functionality like marking, copying, pasting, folding of code, etc. Also editor should be MDI application and should be platform independent (Mostly editor will be run on linux system and X windows). (I shall provide detailed RS (Requirement Specification) once freelancer is decided) For above editor I need some one who can develop it using wxWidgets (scintilla lib ). wxWidgets has already developed libraries for editor functionality. Hence one only has to use them and just add wrapper of rules
I am looking for someone to create a video frame buffer utilizing a Xilinx Spartan 3AN FPGA, Texas Instruments TVP7000 Video ADC, and 64 MB SDRAM. Initial Requirements: * Create a SDRAM controller between RAM and FPGA * Take data (32 bit digital video) from ADC and write to RAM More phases will come, but this is to get started. You may use either VHDL or Verilog. ## Deliverables Rent A Coder requirements notice: As originally posted, this bid request does not have complete details. Should a dispute arise and this project go into arbitration "as is", the contract's vagueness might cause it to be interpreted against you, even though you were acting in good-faith. So for your protection, if you are interested in this project, please work-out ...
I have four algorithms that needs to be converted from the actual programing language C into VHDL or Verilog. Also I need the VHDL/Verilog code, the Simulation and a simple documentation. For more details, post a PM.
I have a FPGA borard, SPARTAN 3E. I split this project in 2 or it can be done in one. 1. First part of the project, is the implementation of 3 C++ codes into VHDL language. Simple pure translation from C++ to VHDL. 2. Seccond part of the project, is creating the VGA interface of the FPGA board, and the PS2 interface of the board too. I need this project very fast, my ultimate deadline is 20.06.2009, first hour in the morning!!! Also 3 days! I need someone to do the first part, also the C++ to VHDL conversion and then the seccond part, the 3 modules and the implementation of the first part with help of the seccond part on my Spartan 3E FPGA board. Please note the maximum Budget is 90$ !!! Please note the final deadline is 20.06.2009, first hour in the...
I have a FPGA borard, SPARTAN 3E. I split this project in 2 or it can be done in one. 1. First part of the project, is the implementation of 3 C++ codes into VHDL language. Simple pure translation from C++ to VHDL. 2. Seccond part of the project, is creating the VGA interface of the FPGA board, and the PS2 interface of the board too. I need this project very fast, my ultimate deadline is 20.06.2009, first hour in the morning!!! Also 3 days! I need someone to do the first part, also the C++ to VHDL conversion and then the seccond part, the 3 modules and the implementation of the first part with help of the seccond part on my Spartan 3E FPGA board. Please note the maximum Budget is 90$ !!! Please note the final deadline is 20.06.2009, first ...
...available for the hardware description languages Verilog and VHDL. These grammars are similar to the ones listed on the grammars web site, and do not generate AST's. These grammers do have embedded actions to perform formatting of the output. In order to implement a variety of features to Verilog and VHDL preprocessors and editors we require AST grammers, tree-walkers and StringTemplates. This project will provide the basic AST structures that will be required to implement these additional features in future projects. The specific requirements for this initial project are: 1. Convert the existing VHDL and Verilog grammars to support AST's, and strip out the formmatting actions. 2. Build a Tree Grammar for VHDL...
Witam, szukam chętnej osoby znającej język VHDL, która podejmie się wykonania 3 zadań w tym języku. Program dowolny gdyż interesuje mnie tylko działający kod. Termin wykonania zlecenia to maksymalnie czwartek wieczór. Oto skrócony opis zadań: 1. Multiplekser o 4 wejściach adresowych - opis komponentowy 2. Transkoder, który wprowadzoną liczbę w dowolnym kodzie (np. BCD 8421 ) pokaże dziesiętnie na 2 wyświetlaczach - opis strukturalny 3. Wyświetlenie na wyświetlaczu 7-segmentowym przesuwającego się w lewo bądź prawo wyrazu 'POLE' - opis strukturalny Po szczegółowe informacje wraz ze skanami treści zadań proszę o kontakt na nr gg 5596522 lub na maila @wp.pl.
Hello! I need a programmer, that can help me for programing a FPGA Board. The board is a "DIGILENT NEXYS 2" , description of the board at this site : <> So, what I need...help me for programing a FPGA Board. The board is a "DIGILENT NEXYS 2" , description of the board at this site : <> So, what I need is following: the board should be conected to a VGA monitor and a PS2 keyboard. I have already 4 very simple programs written in C++ witch solve equations, and I want this 4 programs to be compiled in VHDL .... and I want a little simple menu to choose witch program to use... The programs are very simple and very short, ~15-20 lines... I need this done very fast....
Witam, szukam chętnej osoby, która zrobiłaby 3 zadania w języku VHDL. Zadania są z pewnością proste jednak nie dla kogoś kto ma z tym językiem pierwszy raz do czynienia :) Potrzebuję je na piątek tak więc termin zlecenia to maksymalnie czwartek wieczór. Oto skrócony opis zadań: 1. Multiplekser o 4 wejściach adresowych - opis komponentowy 2. Transkoder, który wprowadzoną liczbę w dowolnym kodzie (np. BCD 8421 ) pokaże dziesiętnie na 2 wyświetlaczach - opis strukturalny 3. Wyświetlenie na wyświetlaczu 7-segmentowym przesuwającego się w lewo bądź prawo wyrazu 'POLE' - opis strukturalny Po szczegółowe informacje wraz ze skanami treści zadań proszę o kontakt na nr gg 5596522 lub na maila @wp.pl.
Hello! I need a programmer, that can help me for programing a FPGA Board. The board is a "DIGILENT NEXYS 2" , description of the board at this site : ...for programing a FPGA Board. The board is a "DIGILENT NEXYS 2" , description of the board at this site : So, what I need is following: the board should be conected to a VGA monitor and a PS2 keyboard. I have already 4 very simple programs written in C++ witch solve equations, and I want this 4 programs to be compiled in VHDL .... and I want a little simple menu to choose witch program to use... The programs are very simple and very short, ~15-20 lines... I need this done very fast.... I pay with Paypal.... Please let Your contact details in the bid !!!
Hi, i need urgent help with this project. Its due in two days. we use xilinix software. and use fpga board. Specs are posted. I can post the vga interface code if you like. Thanks
Please refer to the HDCP spe...unfamiliar: I have written a VHDL HDCP client including the various subunits of the protocol: * Block Module * LFSR Module * Output Module The encoder is pipelined for differing key inputs (16 deep ). The initial block module works without difficulties, however, the LFSR module is currently failed due to problems with the "Shuffle" network. I am looking for someone to update the VHDL code to be compliant with the test cases in the specification. This will require knowledge of LFSRs, pipelining, and good VHDL knowledge. 95% of the code is completed, and all that needs repaired is the LFSR's/Shuffle connection.
Hello! I have a FPGA board modell: DIGILENT NEXYS 2. I need a programmer in Verilog or VHDL, to make a software for this board witch solves non-linear equations... I will specify the bidders the non-linear equations methods I need... The lower offer wins...
This is not a homework or anything. INstructions in attached zip. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows? (depending on the nature? of the deliverables): a)? For web sites or? other server-side deliverables intended...specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform Windows xp Quartu...
Please refer to attached PDF. Requirements: I only need "Phase One" to be implemented from the PDF instructions, dont worry about the rest. I prefer use of State Machines for implementation Its a straight forward assignment with lot of information for help ## Deliverables 1) Complete and fully-functional working pr...request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform Windows XP Quartus (Web Edition) Verilog Code (Verilog HDL file) Implement on DE...
There is a PDF file attached, I just need Part IV and Part V to be implemented. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows? (depending on the nature? of the deliverables): a)? For web sites or? other server-side deliverabl...specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform windows xp or ...
This is a project done for remote temperature monitoring system using verilog and the it is also done using system velilog. the tool to be used is xilinx and it should simulate and working results should be shown using all possible input and outputs. The specification on how exactly it is required is in the attached the molule for the serial transmitter is already done and i am aupplying the code for it which should be included in the main program. The full work as required by the attached document is required ## Deliverables All requirements are provided in the attached file. The deadline before i want everything to be completed is 18th may 2009 before 4:00pm uk time. file is the main file which says what to do and the other files
development of remote temperature monitoring system using verilog hdl to program CPLD cool runner II processor ## Deliverables see attached zip file
For this project I need to build a SISC (Standard Instruction Set Computing) processor in Verilog HDL,Test Bench for the SISC processor,as well as the program which demonstrates the proper execution of 14 SISC instructions(BRA, BRR, AND, OR and etc). Also 5 hand-assembled programs( like division of unsigned numbers and storing them in the memory, multiplying unsigned numbers and storing them in memory, etc) More project details will be provided to a selected programmer.
I NEED VHDL OR VERILOG CODE OF IMAGE PROCESSING SYSTEM ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows? (depending on the nature? of the deliverables): a)? For web sites or? other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software? installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request. 3) All de...
i HAVE MATLAB CODE AND NEED HELP IN CONVERTING MATCODE TO VHDL ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows? (depending on the nature? of the deliverables): a)? For web sites or? other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software? installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request. 3) All d...
vhdl /c++ code of image processing processing any video image--to detrmine its colour,position and other code should take the image input after some time and process it on its own ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package
i have a matlab code that will do analysis of any colourful object like its colour ,parameters.i want to do some changes in this code and want to convert it into c++ or VHDL project involves implementing a image processing system on FPGA microprocessor ARM to determine how many multiplers time required to implement the can we do the parallel processing to increase the i want all this to be done on software OR any other image analysis code implemented on FPGA ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows? (depending on the nature? of the deliverables): a)? For web sites or? other server-side deliverables
PAL/NTSC video is samples at 27 MHz @ 10 bits and stored in a circular buffer, buffer does have a length of two video lines (128us). The video is simply processed and send out to a DAC back into normal PAL/NTSC. FPGA used is XC3S50AN. Your required to write the VHDL Code for the FPGA used. Video Codec used is ADV7202 from Analog devices. Control processor from Microchip is communicating with the FPGA for sending commands (type of processing needed). More details will be given to the winner of the Bid.
...board (board = “Solution Packaging“) supporting: Parallel (“Host-side??) to Parallel-IDE and USB (Target-side) adapter with configuration and control registers at Host-side. These registers will also control the a small 256KB RAM (at FPGA or MCU), Boot_Block access, etc **(see enclosed updated document). **This is an embedded project and coder must have schematic-H/W and code (S/W and optionally VHDL) expertise. Remark: This was a 4 phase project and hereby the first to show: Phase-1 project. Former bidders requsted to place a bid per all four phases. This bid calls for Phase-1 only and after completion by winner/s we will issue the next phase bid and so on. The attached document describes all fours phases. Pls. your attention to bid on phase-1 only. ...
...100K) tested board (board = “Solution Packaging“) supporting: Parallel (“Host-side??) to Parallel-IDE and USB (Target-side) adapter with configuration and control registers at Host-side. These registers will also control the a small 256KB RAM (at FPGA or MCU), Boot_Block access, etc (see enclosed document). This is an embedded project and coder must have schematic-H/W and code (S/W and optionally VHDL) expertise. Remark: This is a 4 phase project. Coder requsted to place a bid per each phase. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web site...
Digital Engineer, FPGA/VHDL/C++, can result in shared ownership of the project. An ongoing hardware development project needs personnel for debugging/completing a design based on FPGA. Job Description Work as a VHDL developer on a hardware development team to complete a leading edge development project building next generation network security systems. Candidates shall meet following qualifications: Good general programming skills Working VHDL knowledge Working C/C++ knowledge GNU tools knowledge Good understanding of computer architecture About Us Inproa Data AB is a Swedish company working with data security and recovery. We have been in this business for over seventeen years. Our methods for data recovery and security belong to the most ad...
**An ongoing hardware development project needs personnel for debugging/completing a design based on FPGA.** **Job Description** Work as a VHDL developer to completing a design based on FPGA. ## Deliverables Candidates shall meet following qualifications: **Xilinx FPGA devices and design toolsets. ****FPGA code design using the VHDL language. Strong architectural design skills. ** Working VHDL knowledge Working C/C++ knowledge GNU tools knowledge Code simulation and verification using a variety of development toolsets. **About Us** Inproa Data AB is a Swedish company working with data security and recovery. We have been in this business for over seventeen years. Our methods for data recovery and security belong to the most advanced in ...
I need the program for an alu model of blackfin processor ADSP BF533. So, that I can run and simulate it using XILINX. It must be synthasizable. You can just e-mail me the code. ## Del...under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform Windows XP and VISTA are the supporting ones. ISE - XILINX of version 8.2i is the software you need. It contains VHDL model aswell. useful links are... When you download xilinx you'll find a tutorial file in the destination folder. It may help you.
Here is the specification: Must be finished by December3.
Witam serdecznie potrzebuje prosty program w jezyku VHDL wiecej informacji na email.
I have a small project that I need done by Verilog that can work on Quartus II software. it basically consists of the mastermind game, where a user inputs a sequence of 4 colours and the other user must guess the 4 sequence of colours by the first user. I have a VGA module already implemented. As I wanted to show this on the screen. so does anyone know how to do this??? I didn't know what to pick for this since Verilog is not listed.
Poszukuję osoby ze znajomością Vhdl-a. Proszę o kontakt w celu omówienia szczegółów.
