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    368 vlsi 搜到的工作,价格货币为 HKD

    I need someone to hello work on a VLSI design using Cadence Virtuso. Needs to be experienced. I will give details on chat. Please bid only if you can do Please, Don’t include the adder. In the published paper, there is two types of energy used as input, in my project I’m using only piezo, so just ignore the adder part. I am adding a picture which can help

    $161 (Avg Bid)
    $161 平均报价
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    I need someone to hello work on a VLSI design using mentor graphics or Cadence Virtuso. Needs to be experienced. I will give details on chat. Please bid only if you can do Please, Don’t include the adder. In the published paper, there is two types of energy used as input, in my project I’m using only piezo, so just ignore the adder part. I am adding a picture which can help

    $107 (Avg Bid)
    $107 平均报价
    2 个竞标

    I need someone to hello work on a VLSI design using mentor graphics or Cadence Virtuso. Needs to be experienced. I will give details on chat. Please bid only if you can do Please, Don’t include the adder. In the published paper, there is two types of energy used as input, in my project I’m using only piezo, so just ignore the adder part. I am adding a picture which can help

    $211 (Avg Bid)
    $211 平均报价
    2 个竞标

    I am looking for VLSI expert now. If you can do it, we can discuss in details on chat.

    $697 (Avg Bid)
    $697 平均报价
    8 个竞标

    I need someone to hello work on a VLSI design using mentor graphics. Needs to be experienced. I will give details on chat. Please bid only if you can do

    $196 (Avg Bid)
    $196 平均报价
    3 个竞标

    I need someone to hello work on a VLSI design using mentor graphics. Needs to be experienced. I will give details on chat. Please bid only if you can do

    $157 / hr (Avg Bid)
    $157 / hr 平均报价
    1 个竞标

    I need someone to hello work on a VLSI design using mentor graphics. Needs to be experienced. I will give details on chat. Please bid only if you can do

    $493 (Avg Bid)
    $493 平均报价
    4 个竞标

    I need someone to hello work on a VLSI design using mentor graphics. Needs to be experienced. I will give details on chat. Please bid only if you can do

    $23 / hr (Avg Bid)
    $23 / hr 平均报价
    5 个竞标

    I need someone to hello work on a VLSI design using mentor graphics. Needs to be experienced. I will give details on chat. Please bid only if you can do

    $180 (Avg Bid)
    $180 平均报价
    7 个竞标

    I need animated video with storyline or concept for promoting our VLSI institute in facebook and Youtube. This should be with audio . Sample : [登录来查看链接] Note : Sample is only for reference .

    $540 (Avg Bid)
    $540 平均报价
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    VLSI Designer 已经结束 left

    I need a designer, who can prepare a diagram for my IOT modules

    $133 (Avg Bid)
    $133 平均报价
    8 个竞标

    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

    $258 / hr (Avg Bid)
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    We have coded and designed a player based on the vs 1005 by vlsi. Now it is nearly finished and there are some small issues to fix. Later there will come more, but we need that for the first step and this is only a small task. The player shall be able to handle that the SD-card is changed. At the moment, when the card is pulled out and another is pushed in, the programm crashes. That shall be fixe...

    $266 (Avg Bid)
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    VLSI design principle 已经结束 left

    questions answer about: - Types of ASIC - Principle Programmable ASIC - Principle of ASIC design

    $298 (Avg Bid)
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    I need animated video with storyline or concept for promoting our VLSI institute in facebook and Youtube. Sample : [登录来查看链接] Note : Sample is only for reference .

    $392 (Avg Bid)
    $392 平均报价
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    Wanted Online FPGA Tutor 已经结束 left

    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

    $822 (Avg Bid)
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    Trophy icon Logo for COMSYS 已经结束 left

    The main objective of COMSYS is to present the latest research and results of scientists related to Machine learning, Computational Intelligence Track, VLSI, Networks and Systems Track, Computational Biology Track, Security Track topics. This conference provides opportunities for the different areas delegates to exchange new ideas and application experiences face to face, to establish business or ...

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    $219
    58 项参赛作品

    VLSI design for Reed Solomon FEC for 198,194 including documentation and explanation. Verilog files and simple testbench to prove the design. ASIC

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    FPGA VLSI DESIGN 已经结束 left

    FPGA implementation - implement lightweight block cipher (Lilliput, SFN)

    $713 (Avg Bid)
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    Project for Iqrasoftware 已经结束 left

    I can help you in Vlsi or MATLAB projects

    $55 / hr (Avg Bid)
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    1 个竞标
    VLSI Microwind. 已经结束 left

    part (a) is already done and attached below, looking for someone to do part (b) which is implementation of part (a) in microwind a. Design and implement the following circuit with four inputs and four outputs using CMOS transistors. • The first output is high when the binary value of the input is less than or equal to7 • The second output is high when the binary value of the input is b...

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    b. Draw the mask layout with Ln = Lp= 0.6 μm, Wn= 4.8 μm and Wp= 8.4 μm using 0.6 μm technology. Also simulate the design using microwind tool and verify the outputs.

    $180 (Avg Bid)
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    VLSI expert required 已经结束 left

    1. a. Design and implement the following circuit with four inputs and four outputs using CMOS transistors. • The first output is high when the binary value of the input is less than or equal to7 • The second output is high when the binary value of the input is between 5 and 12 • The third output is high when the binary value of the input is greater than or equal to 8 • The fou...

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    VLSI project. 已经结束 left

    Looking for an expert in VLSI a. Design and implement the following circuit with four inputs using CMOS transistors. The output is high if there are odd number of ones in the input The output is high if there are even number of ones in the input. The output if there is two consecutive ones in the input. b. Draw the mask layout with Ln = Lp= 0.6 μm, Wn= 4.2 μm and Wp= 10.2 μm using 0.6 &...

    $274 (Avg Bid)
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    3 个竞标
    VLSI project 已经结束 left

    a. Design and implement the following circuit with four inputs using CMOS transistors. The output is high if there are odd number of ones in the input The output is high if there are even number of ones in the input. The output if there is two consecutive ones in the input. b. Draw the mask layout with Ln = Lp= 0.6 μm, Wn= 4.2 μm and Wp= 10.2 μm using 0.6 μm technology. Also simulate ...

    $415 (Avg Bid)
    $415 平均报价
    3 个竞标

    SMEClabs is the research, development and training wing of SMEC, an ISO 9001:2008 certified global solution provider and the Authorized System Integrator of Schneider Electric, VAF, Kangrim boilers,Bosch Rexroth,DEIF,VARD ,Stx [登录来查看链接] are in the field of Industrial, Oil and Gas and marine sector works since 2001. Training in Automation (PLC,SCADA,DCS C-300,HMI),Instrumentation, Embedded & V...

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    5 个竞标

    Hello Sir, I am MTech student in VLSI and embedded systems. I am doing my project on wearable glasses. I am using Texas instruments TMS320C5535 DSP processor for extraction of image from SD card and giving input to the DLPC 2607. Now I am stuck at the programming of DSP. What are your charges for making PCB with components and DSP programming? Pls let me know.

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    Project for Mahmoud G. 已经结束 left

    asynchronous VLSI design

    $2229 (Avg Bid)
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    semi custom VLSI design 已经结束 left

    asynchronous VLSI design for few application

    $8393 - $16787
    $8393 - $16787
    0 个竞标
    VLSI work.. 已经结束 left

    Design and analyze different MOS combinational logic circuits

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    VLSI Magic Project. 已经结束 left

    I have some work related to VLSI Magic, Looking for a professional who can do this task in a very short time. I will share the details in chat

    $1762 (Avg Bid)
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    6 个竞标
    VLSI Magic Project 已经结束 left

    I have some work related to VLSI Magic, Looking for a professional who can do this task in a very short time. I will share the details in chat

    $274 (Avg Bid)
    $274 平均报价
    1 个竞标
    Asynchronous VLSI Design 已经结束 left

    Develop a VHDL or Verilog code using Asynchronous design methodology.

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    Looking for engineer to do a project related to Magic VLSI and IRSIM. work is related to Encoders Multiplexers Demultiplexers Decoders etc will share the further details in chat

    $274 (Avg Bid)
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    VLSI Magic Project 已经结束 left

    I need something to be done so I would preffer a personal discussion

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    Project for Gurbir P. 已经结束 left

    sir my project is fir filter design and implementation on FPGA VLSI .

    $1120 (Avg Bid)
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    VLSI Expert -- 5 已经结束 left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. more details provided in interview. Write some TCL scripts for a software and leave them in the server where the software is installed, as well as all the output reports that result of running those scripts in the server. To access this server employer gave me user/pass. The other requierement was to write the report.

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    NEED VHDL CODE 已经结束 left

    I NEED VLSI CODE VHDL-7-5-Reed-Solomon ENCODER AND DECODER I HAVE SOME CODE JUST NEED TO RUN AND EXPLAIN MAKING SOME CORRECTIONS

    $125 (Avg Bid)
    $125 平均报价
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    VLSI Expert -- 4 已经结束 left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. more details provided in interview. Write some TCL scripts for a software and leave them in the server where the software is installed, as well as all the output reports that result of running those scripts in the server. To access this server employer gave me user/pass. The other requierement was to write the report.

    $1958 (Avg Bid)
    $1958 平均报价
    2 个竞标
    VLSI Expert -- 3 已经结束 left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. more details provided in interview.

    $1566 (Avg Bid)
    $1566 平均报价
    1 个竞标
    vlsi expert -- 2 已经结束 left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. more details provided in interview.

    $235 - $1958
    $235 - $1958
    0 个竞标
    VLSI Expert 已经结束 left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. more details provided in interview.

    $2350 (Avg Bid)
    $2350 平均报价
    1 个竞标
    VLSI Project -- 3 已经结束 left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. Check the following link. [登录来查看链接]

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    VLSI design 已经结束 left

    I need to design VLSI using magic in Ubuntu.

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    1 个竞标
    VHDL and FPGA programming 已经结束 left

    Here projects are implemented in VHDL programming using Xilinx software. B.E/[登录来查看链接] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

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    I am searching for an experienced embedded firmware engineer / software developer with experience in ARM mbed OS who is helping me with writing the firmware for a project incl. the following components: 1) MCU Nordic nrf52 (Fanstel BT832 or BT840) 2) Gyro incl. DMP (Invensense mpu9250/ICM20689 ) 3) Sound decoder (VLSI vs1053b) 4) Serial (SPI) NAND flash storage (Micron MT29F2G01) 5) Touch input...

    $12999 - $25999
    加封 保密协议
    $12999 - $25999
    35 个竞标
    VLSI Layout using lasi7 已经结束 left

    I'll provide the circuit with the dimension of transistor, I need a freelancer to do two layout in Lasi7.

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    This will be educational institute catering various learning needs of students across various fields of education. Such as one of the example is VLSI verification or software testing etc... Logo should be with name "1-Stop EduHub". Tag line should be "Focused to Deliver Quality Learning". And logo image should be somewhere along the line of attached images.

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    Project for David Dundas 已经结束 left

    i am student, working on PD in vlsi domain, i need to improve financial ,so in free time I'm quite to write contents

    $313 / hr (Avg Bid)
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    Hi, I have a problem with my project, I built everything with a problem with one of the bits sum like s0 s1 s2 s3, I am having issue with s2 , it's giving me unknown and I have a carry in which is not identified anyone with a good experience with VLSI should fix it smoothly. I attached IRSIM analyzer photo to illustrate the issue.

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    4 个竞标