We have a zedboard code which takes data from external adc and transfer over ethernet to pc. Everything is working fine. After data acquisition, we are transferring data of around 75k samples of 16 bit each to PC. Its taking around 3 min for transfer. Need work on data transfer rate and improve the same.
• Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env. • Understanding of verification tools like Simulator, Synthesis etc. • Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL • Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc. • Excellent written and verbal interpersonal skills • Self-motivated and great teammate