Verilog / VHDL Jobs

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关于 Verilog / VHDL
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. 雇佣 Verilog / VHDL Designers

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    19 份搜到的工作，货币单位为 HKD
    CDR using recovery methods digitally -- 3 6 天 left
    已验证

    I have an encoder and decoder developed in Verilog and need debugging

    电路设计 电气工程 工程 FPGA Verilog / VHDL
    $210 / hr (Avg Bid)
    $210 / hr 平均报价
    2 个竞标
    立即竞标
    CDR using recovery methods digitally -- 2 6 天 left
    已验证

    I have an encoder and decoder developed in Verilog and need debugging

    电路设计 电气工程 工程 FPGA Verilog / VHDL
    $155 / hr (Avg Bid)
    $155 / hr 平均报价
    3 个竞标
    立即竞标
    CDR using recovery methods digitally 6 天 left
    已验证

    I have an encoder and decoder developed in Verilog and need debugging

    电路设计 电气工程 工程 FPGA Verilog / VHDL
    $117 - $194 / hr
    $117 - $194 / hr
    0 个竞标
    立即竞标
    Design and Implementation of baseband processor for automotive radar system on FPGA 5 天 left

    This project is based on design and implementation of FMCW automotive radar system on Matlab Simulink and calculation of different parameter like speed ,distance and angle and converting signal processing block of radar system into HDL code and verifying the same scenario with same input. Later, optimization of generated HDL code and implementing HDL code into FPGA and verifying it with same inpu...

    电气工程 FPGA LabVIEW 矩阵及数学软件 Verilog / VHDL
    $1298 (Avg Bid)
    $1298 平均报价
    1 个竞标
    立即竞标
    physical design Engineer 5 天 left

    I want to know complete VLSI physical design flow in detail

    SoC Design Verilog / VHDL Very-large-scale integration (VLSI)
    $249 (Avg Bid)
    $249 平均报价
    2 个竞标
    立即竞标
    Design a block diagram for a smart watch using vivado. 5 天 left

    Design a block diagram for a smart watch using vivado.

    电子 FPGA 微控制器 印制板布局 Verilog / VHDL
    $590 (Avg Bid)
    $590 平均报价
    5 个竞标
    立即竞标
    Design a block diagram in vivado 5 天 left

    Design a block diagram for a smart watch using vivado.

    C 编程 电路设计 电子 FPGA Verilog / VHDL
    $117 (Avg Bid)
    $117 平均报价
    2 个竞标
    立即竞标
    Motor Control through dsPIC33CK and interface with LabVIew 5 天 left
    已验证

    I want to control motor with dsPIC33CK and interface with LabVIEW Software.

    Arduino 嵌入式软件 LabVIEW 微控制器 Verilog / VHDL
    $311 (Avg Bid)
    $311 平均报价
    4 个竞标
    立即竞标
    build me a circuit to switch resistance 4 天 left
    已验证

    I have a circuit, that in which I am using a relay to switch resistance if anyone could explain to me the way another possibility with the circuit, without any microcontroller to switch resistance with low cost and size, I want to switch 1.2ohm resistance to the existing circuit.

    电路设计 电气工程 电子 微控制器 Verilog / VHDL
    $148 (Avg Bid)
    $148 平均报价
    10 个竞标
    立即竞标
    Design and Implementation of baseband processor for automotive radar system on FPGA -- 2 4 天 left

    The project is based on designing of automotive radar system using Matlab Simulink block and to perform speed, distance, angle of azimuth and angle of elevation estimation and then performing high level synthesis to generate RTL code of design using Matlab HDL coder tool. Optimization of different parameters like speed and distance using HLS directives of generated HDL code . Implementation and ve...

    电子 FPGA LabVIEW 矩阵及数学软件 Verilog / VHDL
    $1197 (Avg Bid)
    $1197 平均报价
    3 个竞标
    立即竞标
    Computer science logic design 3 天 left
    已验证

    Computer science logic design

    汇编 Computer Science 电气工程 Verilog / VHDL 网站设计
    $684 (Avg Bid)
    $684 平均报价
    18 个竞标
    立即竞标
    Computer Science Arithmetic Logic Unit design 3 天 left
    已验证

    Computer Science Arithmetic Logic Unit design

    汇编 Computer Science 电气工程 软件构架 Verilog / VHDL
    $870 (Avg Bid)
    $870 平均报价
    7 个竞标
    立即竞标
    Design Arithmetic Logic Unit for computer science 3 天 left
    已验证

    Three 32-bit registers RT, RS, RD, 16-bitIMM16, 32-bit Memory Address Register(MAR), 32-Bit Memory Data Register (MDR), design arithmetic logic unit comprised of ADD/SUB and Bitwise operations.

    汇编 Computer Science 电气工程 工程 Verilog / VHDL
    $264 (Avg Bid)
    $264 平均报价
    3 个竞标
    立即竞标
    System engineering -- 2 2 天 left

    Want to buid a matlab or a lingo program

    电气工程 工程 矩阵及数学软件 软件构架 Verilog / VHDL
    $969 (Avg Bid)
    $969 平均报价
    7 个竞标
    立即竞标
    VS, MIPS, LINUX and GDB for Business purpose 2 天 left
    已验证

    VS, MIPS, LINUX and GDB for Business purpose

    汇编 Computer Science Linux Verilog / VHDL Visual Studio
    $85 (Avg Bid)
    $85 平均报价
    3 个竞标
    立即竞标
    Operating system lab 2 天 left
    已验证

    This is Arith matic misp lab. I have attached whole pdf. you have to look pdf and follow the instruction. Please see attach pdf. If you understand the lab fully please send me a chat. Every thing is on pdf.

    Altera Quartus Computer Science Verilog / VHDL
    $54 / hr (Avg Bid)
    $54 / hr 平均报价
    6 个竞标
    立即竞标
    I need a HDL Developer 2 天 left

    Need to create a 8052 softcore on a CPLD which will communicate with some Logic ICs, external SRAM Memory. No restrictions on Timing as such.

    C 编程 软件构架 Verilog / VHDL
    $2673 (Avg Bid)
    $2673 平均报价
    7 个竞标
    立即竞标
    work on the Scilab program 2 天 left

    implementation on scilab of the projected gradient algorithm and the interior penalty algorithm. Do a to describe how to solve an optimization problem with or without constraints

    算法 C 编程 C++编程 矩阵及数学软件 Verilog / VHDL
    $194 (Avg Bid)
    $194 平均报价
    2 个竞标
    立即竞标
    design a instruction set architecture in a microprocessor 7 小时 left

    Design the instruction set architecture of a single cycle processor with 18 bit wide instructions, and data-word width of your choice. need to show the hardware implementation details of the processor. In particular, provide the • Instruction set along with the binary codes • Instruction encoding/decoding logic • Discuss various tradeoffs made in your design to optimize the followin...

    Digital Electronics 电气工程 Electronic Design 微控制器 Verilog / VHDL
    $311 (Avg Bid)
    $311 平均报价
    2 个竞标
    立即竞标
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