Verilog / VHDL 工作与竞赛

Verilog是一种用于半导体和电子设计领域的描述语言,也常用于模拟和模数混合电路中。VHDL则是一种用于电子设计自动化和集成电路的硬件描述语言。如果您的业务涉及Verilog / VHDL,您可以雇佣一些自由职业者完成部分作业。现在就发布您的Verilog/VHDL项目需求,与中意的自由职业者取得联系吧。
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项目/竞赛 描述 竞标数/参赛作品数 技能 已开始 结束 价格(HKD)
Simple Verilog and Arithmatic Logic Unit It is a Simple Verilog and Arithmatic Logic Unit. 7 Verilog / VHDL, 电機工程 Oct 23, 2017 今天6天 20时 $312
Dual axis sun tracking system using myRIO I need someone who could develop the program on labview using myrio to track sun and move the panels accordingly. I am using servo motors. 10 Verilog / VHDL, 微控制器, 电機工程, 嵌入式软件, LabVIEW Oct 22, 2017 Oct 22, 20175天 22时 $1116
Digital system and microprocessor small task -- 2 small task on digital system and microprocessor using verilog amount usd 20 time 1 day 10 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Oct 22, 2017 Oct 22, 20175天 14时 $242
Electrical engineering expert needed to do vhdl code Electrical engineering expert needed to do vhdl code $30 pay 10 工程, 电子, Verilog / VHDL, 电機工程, 学术写作 Oct 22, 2017 Oct 22, 20175天 13时 $408
Custom Verilog design We need to build a custom Verilog design. Please message for further details. 13 工程, Verilog / VHDL, 电機工程, LabVIEW, FPGA Oct 21, 2017 Oct 21, 20174天 23时 $187
project verilog Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 10 C 编程, 工程, Verilog / VHDL, 电機工程, FPGA Oct 21, 2017 Oct 21, 20174天 13时 $94
VLSI design and testability using SPICE/ Verilog/VHDL An applied project may involve using tools such as Spice, Verilog/VHDL, etc. to demonstrate its success 10 Verilog / VHDL, Very-large-scale integration (VLSI) Oct 20, 2017 Oct 20, 20174天 4时 $3637
Logisim Software Tasks Hi I need someone who is good with Logisim Software to complete some tasks. 9 工程, 电子, Verilog / VHDL, 电機工程 Oct 20, 2017 Oct 20, 20173天 23时 $203
Power Generation Simulation using LabVIEW Power Generation Simulation using LabVIEW. Power generation stations will often consist of a number of individual generators where each generates a proportion of the overall station’s output. Need two separate applications. Application 1 and Application 2. 8 矩阵及数学软件, Verilog / VHDL, 电機工程, LabVIEW, Arduino Oct 20, 2017 Oct 20, 20173天 15时 $421
Digital design using Verilog Use Basys 3 Board and Vivado 2016.2 I'll share the rest details 7 Verilog / VHDL, 微控制器, 电機工程, LabVIEW, FPGA Oct 20, 2017 Oct 20, 20173天 14时 $328
VHDL Radio Clock + python script Need help in VHDL everything is mentioned on the PDF 6 电子, Verilog / VHDL, 软件测试, 电機工程, FPGA Oct 19, 2017 Oct 19, 20172天 17时 $360
Project for Gabriel G. I need help with capsim practice rounds 4 项目管理, 电话销售, Excel, 矩阵及数学软件, Verilog / VHDL Oct 18, 2017 Oct 18, 20172天 6时 $195
verilog project making verilog on quartus II (cyclone IV) 11 工程, Verilog / VHDL, 软件构架, 汇编, FPGA Oct 18, 2017 Oct 18, 20172天 $1132
Cloudsim project I want someone to work on programming part in cloudsim that includes migration, Placement, scheduling and power consumption. 2 C 编程, Java, Verilog / VHDL, 软件构架, C++编程 Oct 18, 2017 Oct 18, 20171天 14时 $477
Verilog programming - 18/10/2017 00:34 EDT Simple verilog programming project. Create an ALU with full [链接已删除,请登录查看] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. 14 Verilog / VHDL Oct 18, 2017 Oct 18, 20171天 12时 $780
Verification Of Motion Estimator Using UVM Verification Of Motion Estimator Using UVM(Universal Verification Methodology) 5 Verilog / VHDL, 电機工程, Very-large-scale integration (VLSI) Oct 17, 2017 Oct 17, 20171天 11时 $1857
Verilog programming Simple verilog programming project. Create an ALU with full [链接已删除,请登录查看] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. 5 Verilog / VHDL Oct 17, 2017 Oct 17, 20171天 8时 $695
ASIC Design in Verilog This project is related to Computational Neural Networks 3 矩阵及数学软件, Verilog / VHDL, Neural Networks Oct 17, 2017 Oct 17, 20171天 4时 $1459
VHDL Radio clock everything is going to be explained on the pdf 11 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Oct 17, 2017 Oct 17, 20171天 3时 $308
Design of audio visualiser using DE2-115 Altera board I want to implement an audio visualizer on the screen of the voice spoken through the mic or played using SD card. 4 Verilog / VHDL Oct 17, 2017 Oct 17, 20171天 1时 $1825
Matlab power system Simulation using Simulink -- 2 - 17/10/2017 07:15 EDT My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa 14 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Oct 17, 2017 Oct 17, 201719时 37分 $1064
Matlab power system Simulation using Simulink My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa 9 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Oct 17, 2017 Oct 17, 201717时 51分 $1224
电子, Verilog / VHDL, 微控制器, 电機工程, LabVIEW Oct 16, 2017 Oct 16, 201712时 9分
netlist construction in EE using C++ refactor the sample code by using the c++ 8 C 编程, Verilog / VHDL, C# 编程, 电機工程, C++编程 Oct 16, 2017 Oct 16, 2017结束 $1007
verilog project want verilog code on fpga i want soon 2 工程, Verilog / VHDL, 软件构架, LabVIEW, FPGA Oct 16, 2017 Oct 16, 2017已经结束 $62
ASIC Designs and Development Hello. I am into a project that involves creating PCB / ASIC design with FPGA/CLPD. The specified ASIC Architecture as a product needs to be able calculate one or more algorithms connected through some type of data socket. Performance and power is important. I am interrested to get in touch with a board designer and vhdl developer that have knowledge both with electrical layouts and vhdl. ... 8 工程, 电子, Verilog / VHDL, 电機工程, 印制板布局 Oct 16, 2017 Oct 16, 2017已经结束 $125
veriloghdl code for calculation area THis must implement on quartus( altera FPGA cyclone IV) 3 C 编程, Verilog / VHDL, 微控制器, C++编程, FPGA Oct 16, 2017 Oct 16, 2017已经结束 $999
making verlog hdl code calculataion area in black and white image on fpga ( cyclone IV) 9 C 编程, Verilog / VHDL, 微控制器, 电機工程, C++编程 Oct 16, 2017 Oct 16, 2017已经结束 $968
VHDL Coursework help in VHDL codes ,, everything will be explained later 14 工程, 电子, Verilog / VHDL, 电機工程 Oct 15, 2017 Oct 15, 2017已经结束 $443
fpga software I want to read programmes in FPGA chips 17 C 编程, Verilog / VHDL, 软件构架, FPGA Oct 15, 2017 Oct 15, 2017已经结束 $3223
creation of hardware module using verilog which will be able to communicate with the memory of the processor using Verilog which will be able to communicate with the memory of the processor 4 Verilog / VHDL Oct 14, 2017 Oct 14, 2017已经结束 $484
simple verilog hdl code calculate each area in black and white image 11 C 编程, 工程, Verilog / VHDL, 微控制器, FPGA Oct 13, 2017 Oct 13, 2017已经结束 $367
Simple Verilog Project Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3. 8 工程, 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Oct 13, 2017 Oct 13, 2017已经结束 $187
Color space conversions and FPGA's 3 pages report in two parts on: (i) fundamental information about FPGAs and their programming, and (ii) standard color spaces and formulas for converting those color spaces into other ones. (Plagarism free) finished in 3 days maximum. 9 工程, Verilog / VHDL, 电機工程, FPGA Oct 13, 2017 Oct 13, 2017已经结束 $515
Build software Looking for expert in FPGA and verilog 18 C 编程, Verilog / VHDL, 软件构架, C++编程, FPGA Oct 12, 2017 Oct 12, 2017已经结束 $3746
Statcom in simulink Power electronics expert -- 2 Statcom in simulink Power electronics expert needed 9 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Oct 11, 2017 Oct 11, 2017已经结束 $1281
Want to develop robotic program and test the same with simulation to check feasibility of and automation idea Existing : Manual labours are lifting filled 25 kg bags from stack of machine palletised load (40 bags per wooden pallet, and loading into trucks, containers. Automation solution : Using three axis gantry robot, vacuum lifting end tool and smart programming to create fully automatic truck loading system. All above only on simulation, 3d models to check feasibility of solutions and then to us... 5 矩阵及数学软件, Verilog / VHDL, 软件构架, 软件开发, 编程 Oct 11, 2017 Oct 11, 2017已经结束 $36520
VLSI PROJECTS FIND THE ATTACHED IEEE [链接已删除,请登录查看] REQUIREMENTS 4 Verilog / VHDL, FPGA, Very-large-scale integration (VLSI) Oct 11, 2017 Oct 11, 2017已经结束 $670
Statcom in simulink Power electronics expert Statcom in simulink Power electronics expert needed 9 电子, 矩阵及数学软件, Verilog / VHDL, FPGA Oct 11, 2017 Oct 11, 2017已经结束 $887
Convert a code from Aptech Gauss language into Matlab with Parallel processing. I have a code written in Aptech Gauss program that I want to convert into Matlab and I want the code to run under CUDA power in Matlab. 3 矩阵及数学软件, Verilog / VHDL, 软件构架, CUDA, 软件开发 Oct 10, 2017 Oct 10, 2017已经结束 $1192
Prelab Write VHDL code 7 Verilog / VHDL Oct 10, 2017 Oct 10, 2017已经结束 $211
Altera DE115 - Audio signal processing Record voice , Add and Remove Noise and play back recording. Design and implement the verilog code on an Altera DE2-115 Development Board. Available Hardware Microphones, Speakers 9 Verilog / VHDL, 微控制器, 嵌入式软件, 汇编, FPGA Oct 10, 2017 Oct 10, 2017已经结束 $1762
Audio Signal Processing AIM - Record Audio , Add and Remove Noise and play back audio. To design and implement the Embedded System centred on an Altera DE2-115 Development Board. The project should be based on a Verilog HDL implementation. Available Hardware In addition to the DE2-115 board, the following hardware devices are available. If you wish to do a project requiring hardware support but don’t see the... 7 Verilog / VHDL, 微控制器, 电機工程, 嵌入式软件, FPGA Oct 10, 2017 Oct 10, 2017已经结束 $3969
Sequence Diagram There is a service class called PurchaseOrder that is called when a customer makes a purchase. It has a public method purchase(Account, Order). It does the following. a. Call [链接已删除,请登录查看]() b. Call [链接已删除,请登录查看](Account) c. Call [链接已删除,请登录查看]() d. [链接已删除,请登录查看]() calls [链接已删除,请登录查看](amount) which makes the payment e. Call [链接已删除,请登录查看](Order) which saves the order f. Call [链接已删除,请登录查看]() whic... 6 Verilog / VHDL, 软件构架, PLC 与 SCADA, 有限元分析, 工程制图 Oct 10, 2017 Oct 10, 2017已经结束 $289
Matlab Program for Harmonics Analysis for a sampled data (Data in excel format) Need a Matlab program to perform Harmonics Analysis for a sampled data (data in Excel format). Matlab Codes must structured to read data from Excel file. Please find the attached Excel file [链接已删除,请登录查看] 22 Excel, 矩阵及数学软件, Verilog / VHDL, 软件构架, 软件开发 Oct 7, 2017 Oct 7, 2017已经结束 $169
UML/MARTE modeling I want to build an interface(which consists of rules) to transform any MML model to a UML-MARTE model using AGG(algebraic graph transformation). 1 Verilog / VHDL, UML 设计, 有限元分析, SAS, 计算机图形辅助三维交互式应用 Oct 7, 2017 Oct 7, 2017已经结束 $4578
matlab report making 10 pages minimum hi discussion via chat no front milestone need it in 12 hrs 10 mages maximum paper should be in IEEE formats no plagiarism is there.. please give a good quote 10 矩阵及数学软件, Verilog / VHDL, LaTeX, 数学, 物理 Oct 7, 2017 Oct 7, 2017已经结束 $375
Matlab Write a Function for Forward Kinematics of the RPR Robot Input Format are the joint angles in radian, as shown in the figure is the extension of the prismatic joint in inches, as shown in the figure Output Format R is a 3x3 rotation matrix representing (Note: where represents a point in frame x) pos is a 4x3 matrix where each row contains the x,y,z coordinates represented as [x y z] in matrix form. Each row is the x,y,z coordinates of a point... 16 矩阵及数学软件, Verilog / VHDL, 软件构架, 有限元分析, 软件开发 Oct 7, 2017 Oct 7, 2017已经结束 $296
String compare algorithm need an algorithm that would compare two long strings delimited by | 3 矩阵及数学软件, Verilog / VHDL, 算法, CUDA, 机器学习 Oct 7, 2017 Oct 7, 2017已经结束 $15296
Cryptoanalysis - Cryptograpgy - C programming I am looking for someone to write me a code in c that will test the cryptographic strength of the passwords. I can share more specific instructions and dummy passwords. I need a simple program. 9 C 编程, Verilog / VHDL, 软件构架, 序言, C++编程 Oct 6, 2017 Oct 6, 2017已经结束 $538
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