Verilog / VHDL 工作与竞赛

Verilog是一种用于半导体和电子设计领域的描述语言,也常用于模拟和模数混合电路中。VHDL则是一种用于电子设计自动化和集成电路的硬件描述语言。如果您的业务涉及Verilog / VHDL,您可以雇佣一些自由职业者完成部分作业。现在就发布您的Verilog/VHDL项目需求,与中意的自由职业者取得联系吧。
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项目/竞赛 描述 竞标数/参赛作品数 技能 已开始 结束 价格(HKD)
Verilog Servo controller I'm looking for someone who can write me a verilog HDL code for a servo controller 2 C 编程, Verilog / VHDL, 微控制器, 电機工程, FPGA Feb 18, 2018 今天6天 20时 $250
AI Based Chip Design For video codec h.264 for face recognition in cloud and verify output on Xilinx FPGA Kit write an AI Algorithm for video codec h.264 and design Chip, after design chip of AI Based video codec h.264 you can verify out put on Xilinx FPGA Kit for face recognition in cloud iam expecting this project to finish on or before 26th feb2018 regards D RAMANNA [Removed by Freelancer.com Admin for offsiting - please see Section 13 of our Terms and Conditions] BANGALORE-INDIA 0 平面设计, 徽标设计, 电子, Verilog / VHDL, 电機工程 Feb 18, 2018 今天6天 14时 -
Enlarge a Circuit Design I want to make a timing light like those that are used to set the ignition timing on an engine with a spark plug. I need to be able to delay the flash of the light from zero degrees to 720 degrees so that I can video what is happening to mechanisms on an engine while they are running without using a high speed camera. The engine will be running up to 8,000 RPM. I have found an example of ... 16 工程, 电子, Verilog / VHDL, 微控制器, 电機工程 Feb 17, 2018 Feb 17, 20185天 23时 $1494
need help with mplab project please give me full code for this project. using MPLAB software and production must be successful. make the PCB design. 5 电子, Verilog / VHDL, 微控制器, 电機工程, 印制板布局 Feb 17, 2018 Feb 17, 20185天 16时 $285
Electronic Engineer We require an electronic engineer who is skilled in: FPGA Programming (VHDL) PicoBlaze embedded processor (Assembler) DWIN Technology TouchScreen 7 C 编程, 电子, Verilog / VHDL, 微控制器, 电機工程 Feb 16, 2018 Feb 16, 20184天 21时 $241
FPGA Based NMR Spectrometer design Need to design a FPGA based NMR Spectrometer for NMR Applications. Phase 1 : Interface high speed ADC and DAC with Altera FPGA and write the software for generating RF pulses and Capture Echo Signal from ADC. See the attached similar work for more details. 10 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Feb 16, 2018 Feb 16, 20184天 12时 $62143
Design an analog to digital convereter Aim is to design a successive approximation register based analog to digital converter using cadence tool (any vlsi back end tool) 10 工程, 电子, Verilog / VHDL, 微控制器, 电機工程 Feb 16, 2018 Feb 16, 20184天 6时 $7906
adc ltc2308 in vhdl altera deo nano soc cyclone 5 board It is a basic project but since I've never worked with on FPGA before, I think someone with experience is a wise choice. The project is basically read the ADC signal from onboard adc ltc2308 and send it to the DAC. While ADC (ltc2308 ) is 12bit 7 电子, Verilog / VHDL, 微控制器, 电機工程, 电路设计 Feb 12, 2018 Feb 12, 20189时 15分 $633
need someone for FPGA work I would like someone to help me build a simple FPGA Kernel for a certain gaming system. I would like your help to improve a FPGA project we are using Altera Quartus programming software i have attached a QAR file First of all, compile it to a POF file and then send it to me and let me examine it and I will give you more instructions on how to proceed. It's not very complicated Let me ask... 9 C 编程, 电子, Verilog / VHDL, 微控制器, FPGA Feb 12, 2018 Feb 12, 20189时 9分 $1203
An expert in FPGA is required I would like someone to help me build a simple FPGA Kernel for a certain gaming system. 4 C 编程, Verilog / VHDL, 微控制器, 电機工程, FPGA Feb 12, 2018 Feb 12, 20188时 42分 $1168
FPGA QAR Project I have a QAR file that I cannot compile into a POF or PLD file, I would like someone with experience in FPGA to do it. It must be someone with real good knowledge of FPGA. 14 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Feb 12, 2018 Feb 12, 20188时 38分 $3850
Help with plptools needed need perfect work Help with plptools needed need perfect work.. All the details would be given on the chat... Need to submit it till midnight today... 2 矩阵及数学软件, Verilog / VHDL, 微控制器, 数学, , 汇编 Feb 11, 2018 Feb 11, 20182天 14时 $587
FPGA work .... I would like someone to help me build a simple FPGA Kernel for a certain gaming system. 5 C 编程, 电子, Verilog / VHDL, 微控制器, FPGA Feb 11, 2018 Feb 11, 2018已经结束 $211
FPGA CONSOLE I would like someone to help me build a simple FPGA Kernel for a certain gaming system. 5 C 编程, 电子, Verilog / VHDL, 微控制器, FPGA Feb 11, 2018 Feb 11, 2018已经结束 $160
OFDM/256QAM Modulation/Demodulation and Forward Error Correction in Matlab/Xilinx FPGA IP We are looking for develop and implement OFDM / 16QAM, 32QAM, 64QAM , 256QAM Modulation / Demodulation algorithm with Matlab and implement it on Xilinx Zynq FPGA . 1- BW : tunable upto 40Mhz . 2- FEC : LDPC or Reed solomon . 11 工程, 矩阵及数学软件, Verilog / VHDL, 电機工程, LabVIEW Feb 9, 2018 Feb 9, 2018已经结束 $20581
Use edaplayground to run a carry lookahead adder need a 4-bit carry look ahead adder to be coded in system Verilog using edaplayground. 1) write system Verilog model for CLA 2) parameterize for N bits 3) generate/write test bench that works 11 C 编程, Verilog / VHDL, 微控制器, 软件构架, FPGA Feb 8, 2018 Feb 8, 2018已经结束 $188
Controller (Microprocessor Based) Design for Transport Refrigeration System Design , Prototyping of Controller (Microprocessor Based) Design for Transport Refrigeration System to control a system powered by diesel engine based power train and comprising of a Vapour Compression Cycle Refrigeration System comprising of Refrigeration Compressors , Condensors ,Evaporators , heaters etc 7 电子, Verilog / VHDL, 电機工程, 印制板布局, 电路设计 Feb 8, 2018 Feb 8, 2018已经结束 $5262
Steganography - open to bidding I need a C# based Desktop Applications With Following Modules The Encryption Module 1. Registration: - To access the core system, user first need to register themselves by providing required details. 2. Login: - After registration, user may login into the system. 3. Algorithm Selection: - Here, user will select the algorithm such as DES (Data Encryption Standard), AES (Advance Encryption Standa... 7 矩阵及数学软件, Verilog / VHDL, 算法, 印制板布局, 机器学习 Feb 7, 2018 Feb 7, 2018已经结束 $2096
CONFIGURATION OF ADS 5263 EVM WITH ZC702 OR KC705. i have ADS5263 EVM board, and i connected that board with xilinx zc702 via ADC FMC adapter. i tried to write code for that i failed to generate bit stream based on xilinx application note xapp524. i need help to sort out the problem of clock multi region routing. 5 Verilog / VHDL Feb 6, 2018 Feb 6, 2018已经结束 $1176
VHDL Sequence Detector 32 bit Design a sequence detector for 32 bit with counter 5 Verilog / VHDL, 软件构架 Feb 6, 2018 Feb 6, 2018已经结束 $712
integration wsn with clouds using cooja i want a specialist in cloud integration with wsn and have experience in cooja. 9 Java, 工程, 矩阵及数学软件, Verilog / VHDL, C++编程 Feb 6, 2018 Feb 6, 2018已经结束 $798
FIR Filter Reference Design in Verilog We are looking for a FIR filter design in Verilog with the following requirements: - 16-bit input, 16-bit fixed coefficient - 39-bit output - 256 taps Please provide 2 implementations: 1. serial implementation using 1 multiplier 2. partial parallel implementation with 4 multiplers 5 Verilog / VHDL, FPGA Feb 4, 2018 Feb 4, 2018已经结束 $1722
Simple MIPS interpretor Want someone to finish a MIPS project. The project will be required to be finished by the end of the day 8 C 编程, Verilog / VHDL, 软件构架, 汇编, x86/x64 汇编 Feb 4, 2018 Feb 4, 2018已经结束 $407
Recursive karatsuba multiplier (16bit) I need a verilog code for recursive karatsuba multiplier for 16bit signed integers. 6 Verilog / VHDL, 数字设计 Feb 2, 2018 Feb 2, 2018已经结束 $1523
Pthread and OpenMP I have some simple code that I want to compare in OpenMP and pThread to see which is more performant. 1 C 编程, Java, Verilog / VHDL, C++编程, 汇编 Jan 31, 2018 Jan 31, 2018已经结束 $274
dead reckoning Indoor positioning system we want to develop an indoor positioning system using pedestrian dead reckoning method. we are using STM32F469NI microcontroller. using only accelerometer and gyroscope. we have successfully collected the data for accelerometer and gyroscope. so is it possible to employ these data in embedded platform (keil u-vission) to develop the system. other possibility is to save the data in SD card and use ... 15 矩阵及数学软件, Verilog / VHDL, 电機工程, LabVIEW, Arduino Jan 30, 2018 Jan 30, 2018已经结束 $1541
Petalinux on ZC706 I am looking for someone who has done work on Petalinux on ZC706 or Zedboard. The person MUST have done projects of Ethernet, PS Ram usage, external permanent memory storage using PCIe based drive, SPI control. I need to develop a project using above features. 1 Verilog / VHDL, FPGA Jan 29, 2018 Jan 29, 2018已经结束 $1299
ddr sdram controller i want to do some modification to controller i.e either adding a module to it or pipeling it. 3 Verilog / VHDL Jan 20, 2018 Jan 20, 2018已经结束 $1761
build a mips recursive quicksort use recursive way to write quicksort in mips, the c code will be offered 9 C 编程, Verilog / VHDL, C++编程, 汇编, x86/x64 汇编 Jan 17, 2018 Jan 17, 2018已经结束 $321
Matlab Simulation-Impulse Voltage generation Need to modify a schematic(.mdl) to get desired results. The .mdl schematic is attached [链接已删除,请登录查看] need to modify the design to get proper output like Figure 4 12 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Jan 10, 2018 Jan 10, 2018已经结束 $331
need a VHDL expert asap vhdl expert needed asap to run a code 16 工程, 电子, Verilog / VHDL, 电機工程, FPGA Jan 10, 2018 Jan 10, 2018已经结束 $154
License Plate Detection Using VHDL I'm building a license plate detection system, and concept has been proven using MATLAB. The current challenge is to implement the design on an Altera DE Board FPGA using VHDL. At this point, because of time constraints I like to ask for ur assistance in the following areas I seek someone who could help Implement the design on an FPGA. Attached is the matlab code 8 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Jan 9, 2018 Jan 9, 2018已经结束 $4467
Edge detection on Altera DE2-115 Hello, i want to create project using altera DE2-115 board to detect edges on 3 image using sobel filter and show they ober VGA 640x480. To choose which image should be apear is needed 2 swtich. i have done some algorithm with matlab and now i have to implement it on altera. Thanks 16 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, LabVIEW Jan 6, 2018 Jan 6, 2018已经结束 $5039
This task need to be developed using MATLAB....A cicuit bsed on fuzzy logic to detect different kind of faults L-G,L-L,LLL etc. Fuzzy logic based fault detection 9 工程, 矩阵及数学软件, Verilog / VHDL, 算法, 电機工程 Jan 6, 2018 Jan 6, 2018已经结束 $274
SFP communication with FPGA Coding required for FPGA to SFP communication 13 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Jan 6, 2018 Jan 6, 2018已经结束 $7017
VHDL for programming FPGA board Hi, I run a small sales business in the video game industry. I am looking for someone with VHDL experience to assign pins on an FPGA board for an old video game system, to a new pre-designed break out board to allow the system to use HDMI. Please contact for details. 18 Verilog / VHDL, FPGA Jan 2, 2018 Jan 2, 2018已经结束 $993
FPGA Design in VHDL Design of FPGA to serve as a memory mapped resource for a local processor module. The processor interface is a memory mapped address/data bus. The FPGA design contains registers, counters and data path functions. System clock frequency is 25MHz. No internal processor is used within the FPGA. An external SRAM is required for expanded data storage. The target FPGA is the Microsemi ProASIC3E. 10 Verilog / VHDL, 设计 Jan 2, 2018 Jan 2, 2018已经结束 $53491
Project for Varun V. Hi Varun V., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 1 C 编程, Linux, Verilog / VHDL, 嵌入式软件, Jan 1, 2018 Jan 1, 2018已经结束 $1956
Work with Digital Electronic and Analogue... Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 11 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 28, 2017 Dec 28, 2017已经结束 $203
Work with Digital Electronic and Analogue. Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 11 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 28, 2017 Dec 28, 2017已经结束 $266
Work with Digital Electronic and Analogue Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 13 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Dec 28, 2017 Dec 28, 2017已经结束 $258
Work with Digital Electronic and Analogue Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 13 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 27, 2017 Dec 27, 2017已经结束 $360
Convert some VHDL to Verilog Contact me for more details. All I need done is porting some VHDL to Verilog. 18 工程, Verilog / VHDL, 微控制器, 软件构架, FPGA Dec 23, 2017 Dec 23, 2017已经结束 $923
ASIC Design-Verification article on UVM Dear ASIC Verification Experts, I am looking for ghost writer who is from ASIC verification background. I want a unique article which tries to explain why we need to use UVM (Universal Verification Methodology). The title of the article will be similar as this. "If SystemVerilog is so good, why do we need the UVM? ". The article needs to start by answering this question in title. The... 3 Verilog / VHDL Dec 23, 2017 Dec 23, 2017已经结束 $782
vhdl code using altera Design a digital system that will generate police or unbalance siren sound 9 工程, Verilog / VHDL, 微控制器, 电機工程, FPGA Dec 22, 2017 Dec 22, 2017已经结束 $1025
Designing Pipelined RISC 32-bit processor by Logisim simulator - 22/12/2017 12:13 EST Objectives :  Using the Logisim simulator  Designing and testing a RISC 32-bit processor Instruction Set Architecture In this project, you will design a simple 32-bit RISC processor with sixteen 32-bit general purpose registers: R0 through R15. R0 is hardwired to zero and cannot be written, so we are left with fifteen registers. There is also one special-purpose 24-bit program counter (PC)... 7 工程, 电子, Verilog / VHDL, 电機工程, 电路设计 Dec 22, 2017 Dec 22, 2017已经结束 $1072
FPGA Project (VHDL floating and real number mathematical operations using Simulink MATLAB) I need a vhdl program allowing FPGA to do aritmetic calculations with real values. For instance summing, substracting, dividing and multiplying 2 real number values as follows: (2.32 + 3.65; 2.32 - 3.65; 2.32/3.65 ; 2.32*3.65) I assume it suppose to be done using some toolbox on MATLAB ( System Generator Toolbox) This code should work on Xilinx Spartan 6. I want the code written simp... 10 矩阵及数学软件, Verilog / VHDL, 电機工程, LabVIEW, FPGA Dec 21, 2017 Dec 21, 2017已经结束 $508
Vhdl and test bench for flip flop I need to build a t flip flop in vhdl and write a test bench for it which shows simulation results then using t flip flop implement 4 bit ripple binary counter in a structural method in vhdl and write a test bench and show simulation results it's a report in PDF 8 Verilog / VHDL Dec 20, 2017 Dec 20, 2017已经结束 $532
Parking meter  The project is to design and implement a parking meter. o When you add a coin to the parking meter, time is added during which you can legally park your car. The meter shows the remaining time in a unit of second continuously, and stops at zero.  Types of coins and their worth Pushbutton 0 (PB0) Add 30 seconds Pushbutton 1 (PB1) Add 60 seconds Pushbutton 2 (PB2) Add 120 seconds Pushbutto... 7 Verilog / VHDL Dec 19, 2017 Dec 19, 2017已经结束 $172
Microcontroller design Design and implementation of controller with VHDL in FPGA 13 电子, Verilog / VHDL, 微控制器, FPGA Dec 19, 2017 Dec 19, 2017已经结束 $1112
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