ok before we had a paper to review about floating point adder in fpga i already did but there is the furue work of that paper talking about specific topic for improvment if u could help me with it (far and close path algorithms).
using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C , C++
I need code for zero crossing detection, synced with pwm generator with fixed duty cycle but variable frequency in esp-idf. I need it urgently Its a signal generator like square wave or pwm with fixed 50% duty cycle, but its frequency needs to be varied from 500 to 100Khz (might be done using ledc_timer_1_bit) but when there is zero crossing, its signal needs to be stopped so that igbt should'nt conduct at zero crossing,
the concept, design methodology, architecture, circuit gate & performance (speed), and fabrication techniques for integrated circuits (ICs). The main focus is on design for complementary metal-oxide-semiconductor (CMOS) technology.