Verilog / VHDL Jobs

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关于 Verilog / VHDL
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. 雇佣 Verilog / VHDL Designers

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    13 份搜到的工作，货币单位为 HKD
    Use ethernet interface of the Zedboard to display the result of a a simple 16 bit adder on the screen (ssh, putty) 6 天 left
    已验证

    I have one zed board with ethernet on it. I one to display the output of the adder over the ethernet. Adder is not an issue you can download it from anywhere, should be in VHDL, then the output of the adder should be transferred to the ethernet and then use the telnet or putty to display the Output.

    C 编程 电子 FPGA Verilog / VHDL
    $4358 (Avg Bid)
    $4358 平均报价
    4 个竞标
    立即竞标
    VHDL Expert needed -- 4 5 天 left
    已验证

    communication between two usarts

    FPGA Verilog / VHDL
    $861 (Avg Bid)
    $861 平均报价
    2 个竞标
    立即竞标
    VHDL implementation of UART 4 天 left

    I need vhdl code for uart to be implemented on basys 3 my budget is 150 usd max

    C 编程 电气工程 FPGA 微控制器 Verilog / VHDL
    $868 (Avg Bid)
    $868 平均报价
    12 个竞标
    立即竞标
    VHDL coding of LVDS between two FPGA`s 4 天 left

    I need a VHDL code of LVDS transmission between two FPGA`s. It is a 4 lane LVDS operating at 833.33MHz to transfer information from USART of 1st FPGA to USART of 2nd FPGA.

    C 编程 电气工程 FPGA 微控制器 Verilog / VHDL
    $434 (Avg Bid)
    $434 平均报价
    4 个竞标
    立即竞标
    VHDL Expert needed 4 天 left
    已验证

    I need to write VHDL code for LVDS transmission between two FPGAs. Please ping me if you are familiar with this.

    电气工程 电子 工程 FPGA Verilog / VHDL
    $233 (Avg Bid)
    $233 平均报价
    3 个竞标
    立即竞标
    need VHDL code expert 3 天 left

    need VHDL code expert .........

    C 编程 电气工程 FPGA 微控制器 Verilog / VHDL
    $163 (Avg Bid)
    $163 平均报价
    7 个竞标
    立即竞标
    compression and decompression vhdl code 3 天 left

    Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...

    C++编程 电气工程 FPGA 矩阵及数学软件 Verilog / VHDL
    $1124 (Avg Bid)
    $1124 平均报价
    5 个竞标
    立即竞标
    Verilog/VLSI experts 2 天 left

    Looking for VLSI experts having strong digital electronics and verilog concepts

    电气工程 电子 FPGA 微控制器 Verilog / VHDL
    $613 (Avg Bid)
    $613 平均报价
    8 个竞标
    立即竞标
    vlsi front end experts 2 天 left

    Looking for vlsi frontend experts with strong basics in digital electronics

    Digital Electronics 电子 工程 Verilog / VHDL Very-large-scale integration (VLSI)
    $109 (Avg Bid)
    $109 平均报价
    5 个竞标
    立即竞标
    simple snake fpga 1 天 left

    design very simple basic snake game in quartus. Provide me with the verilog code ,state diagram, design schematic, all codes and instructions for self implementation.

    FPGA FPGA Coding Verilog / VHDL
    $47 / hr (Avg Bid)
    $47 / hr 平均报价
    4 个竞标
    立即竞标
    fpga snake game In quartus 1 天 left

    design very simple basic snake game in quartus. Provide me with the verilog code ,state diagram, design schematic, all codes and instructions for self implementation.

    FPGA FPGA Coding Verilog / VHDL
    $1272 (Avg Bid)
    $1272 平均报价
    14 个竞标
    立即竞标
    pic16f877a interfave with sd card 1 天 left

    i just need the sd card initialization code to interface with pic16f877a couple of code lines thats it

    Arduino 电气工程 电子 微控制器 Verilog / VHDL
    $217 (Avg Bid)
    $217 平均报价
    5 个竞标
    立即竞标
    AHB System verilog 1 天 left

    I want implementation of AHB protocol using one master three slave architecture in Sytem verilog (test bench with generator, driver,monitor, scoreboard)

    Verilog / VHDL
    $620 (Avg Bid)
    $620 平均报价
    2 个竞标
    立即竞标
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