Verilog / VHDL 工作与竞赛
Verilog是一种用于半导体和电子设计领域的描述语言，也常用于模拟和模数混合电路中。VHDL则是一种用于电子设计自动化和集成电路的硬件描述语言。如果您的业务涉及Verilog / VHDL，您可以雇佣一些自由职业者完成部分作业。现在就发布您的Verilog/VHDL项目需求，与中意的自由职业者取得联系吧。
浏览Freelancer上的工作
| 项目/竞赛 | 描述 | 竞标数/参赛作品数 | 技能 | 已开始 | 结束 | 价格（HKD） | |
|---|---|---|---|---|---|---|---|
| Floating Point on DSP48E1 | I need to implement floating point single precision algorithm (add,sub,mul,div)(standar IEEE754) on unit DSP48E1. I need a File Register on 48bit, a priority encoder on 32b, an exponent unit where is stock the sign and exponent and a sequencer(Delay Mealy automata) who give the comand to DSP. Can anybody help me? Thank you! | 4 | Verilog / VHDL, FPGA | Apr 21, 2018 | 今天6天 20时 | $1815 | |
| MIPS Computer Design by Verilog HDL | I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL | 14 | 工程, Verilog / VHDL, 汇编, 数字设计, FPGA | Apr 20, 2018 | 今天6天 1时 | $1114 | |
| need to implement an ieee paper using verilog or vhdl. -- 2 | would like to get the implementation of given ieee paper using verilog/vhdl within 15 days | 3 | Verilog / VHDL | Apr 20, 2018 | Apr 20, 20185天 22时 | $1119 | |
| 200418_Verilog | All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours | 4 | 电子, Verilog / VHDL, 电機工程 | Apr 20, 2018 | Apr 20, 20185天 20时 | - | |
| Conceive SDR GnuRadio blocs | This project aims at conceiving GNU-Radio blocs for receiving / transmitting modulated radio messages using Software Defined Radio (SDR). I need a software component lib called "gr-beaglesdr" of a software-defined radio receiver and transmitter combined with suitable hardware device BeagleSDR. It can be used to listen to or display data from a variety of radio transmissions and also send... | 4 | Linux, 电子, Verilog / VHDL, 微控制器, 电機工程 | Apr 20, 2018 | Apr 20, 20185天 16时 | $5483 | |
| Implementing Bit stuffing in verilog | Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's | 8 | 工程, Verilog / VHDL, 微控制器, 电機工程, FPGA | Apr 20, 2018 | Apr 20, 20185天 12时 | $248 | |
| Edge detection by using laplacian | I want a freelancer for making a project who have strong knowledge of mpi and Openmp c++.If any one interested let me know so we can discuss it further Your task is to implement an initial serial version of the program, where it takes an image as an input and then produces an output image after applying the stencil matrix(Laplacian ) on the input image. Then, you should try to optimize the co... | 1 | C 编程, Verilog / VHDL, 软件构架, CUDA, C++编程 | Apr 19, 2018 | Apr 19, 20185天 6时 | $1162 | |
| Sending and receiving tcpip xgmii packets over SFP+ | This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server. | 3 | Verilog / VHDL, FPGA | Apr 19, 2018 | Apr 19, 20184天 23时 | $3412 | |
| plc program and hmi design Simulation | I have Program pLc program and Hmi design for academics project just to simulating the code with software need basic help | 10 | 工程, 电子, Verilog / VHDL, 微控制器, 电機工程 | Apr 19, 2018 | Apr 19, 20184天 20时 | $157 | |
| develop Simple SW to write on the IC Card/Server | I have IC cards or integrated chip cards that i needed to write on them. So, i am looking for simple SW and support for successful testing of this beta version design. My design and solution is almost the same as access control however it has its own different use cases. So, let’s assume that I need to create SW solution for access control within a hotel or company using IC card i... | 4 | C 编程, 电子, Verilog / VHDL, 微控制器, 印制板布局 | Apr 19, 2018 | Apr 19, 20184天 17时 | $2228 | |
| translate C++ code in systemc. | translate c++ code in systemc and implement constrained random verification methodology. | 6 | C 编程, Verilog / VHDL, 软件构架, C++编程, Very-large-scale integration (VLSI) | Apr 19, 2018 | Apr 19, 20184天 17时 | $329 | |
| build a software | translate c++ code in systemc. and implement constrained random varification methodology. | 2 | Verilog / VHDL, 软件构架, C++编程, Very-large-scale integration (VLSI) | Apr 19, 2018 | Apr 19, 20184天 16时 | $337 | |
| Create a DLX Data Path Using VHDL | Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code. | 7 | Verilog / VHDL, 微控制器, 软件构架, 汇编, FPGA | Apr 18, 2018 | Apr 18, 20184天 8时 | $1514 | |
| build a software | translate a C++ code in systemc module. | 3 | C 编程, Verilog / VHDL, C++编程 | Apr 18, 2018 | Apr 18, 20184天 4时 | $243 | |
| convert the C++ language code in systemc. | you have to translate C++ code in systemc language. | 3 | C 编程, Verilog / VHDL, 软件构架, C++编程 | Apr 18, 2018 | Apr 18, 20184天 2时 | $259 | |
| Do VHDL project on the ModelSim | I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir... | 11 | 工程, 电子, Verilog / VHDL, 电機工程, FPGA | Apr 18, 2018 | Apr 18, 20183天 21时 | $1200 | |
| SoundLocator | Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position | 14 | Java, 电子, 安卓, Verilog / VHDL, FPGA | Apr 18, 2018 | Apr 18, 20183天 18时 | $4856 | |
| Serializer & Desrializer Implementation using ZC706 and MTX | Serializer & Desrializer Implementation using ZC706 and MTX | 6 | Verilog / VHDL, FPGA | Apr 17, 2018 | Apr 17, 20183天 10时 | $227 | |
| OpenCL FPGA Code modification | I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [链接已删除，请登录查看] Please respond directly with any questions such as specific mining software and such. | 8 | C 编程, Verilog / VHDL, 密码学, OpenCL, FPGA | Apr 17, 2018 | Apr 17, 20183天 5时 | $18136 | |
| Circuit at logism | implement a digital circuit in Logisim for a door lock. | 3 | 电子, Verilog / VHDL, 微控制器, 电機工程, 电路设计 | Apr 17, 2018 | Apr 17, 20183天 1时 | $196 | |
| expert in vivado vhdl needed | expert in vivado and vhdl needed asap | 8 | 工程, Verilog / VHDL, 微控制器, 电機工程, FPGA | Apr 17, 2018 | Apr 17, 20182天 22时 | $197 | |
| digital logic design circuit in logisim | there should be A and B inputs and the circuit should check if the A is divisible by B or not. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b). we have only 30 minutes to do. | 8 | 工程, 电子, Verilog / VHDL, 电機工程, 电路设计 | Apr 17, 2018 | Apr 17, 20182天 20时 | $965 | |
| digital circuit in logisim | we should draw a circuit in logisim. there should be 2 input like A and B. the circuit should check if A is dibisible by B or not. you should work with ALU. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b) | 6 | 电子, Verilog / VHDL, 微控制器, 电機工程, 电路设计 | Apr 17, 2018 | Apr 17, 20182天 20时 | $165 | |
| Signal Peak Detector, Digital Design - Command Processor | I am currently working on peak detector using VHDL entry (Modelsim and Xilinx), to design logic design in FPGAs to fulfill my free time. There are two parts, which are command processor and data processor. However, I have completed the data processor part, so only command processor left and I have no idea how to complete it. I plan to accomplish this task by next Sunday, 22nd April before I starte... | 7 | 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 | Apr 17, 2018 | Apr 17, 20182天 20时 | $359 | |
| Circuit in Logism | Given two 4-bit integers, A and B, build a circuit that can outputs 1 if A is divisible by B, or 0 otherwise. It should be done using 4 bit ALU | 8 | 工程, 电子, Verilog / VHDL, 电機工程, 电路设计 | Apr 17, 2018 | Apr 17, 20182天 18时 | $510 | |
| Logisim Digital Logic Design | using four bit ALU, given two numbers A and B we need to find if A is divisible by B | 15 | 工程, 电子, Verilog / VHDL, 电機工程, FPGA | Apr 17, 2018 | Apr 17, 20182天 17时 | $612 | |
| Neural Network on an FPGA | I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware. | 4 | C 编程, Verilog / VHDL, 机器学习, FPGA, Neural Networks | Apr 17, 2018 | Apr 17, 20182天 12时 | $1361 | |
| CRYPTO MINING using VHDL in FPGA | Details later.. I will check your BASIC.. And then recruit You | 3 | Verilog / VHDL, 矿业工程, 数字设计, FPGA | Apr 15, 2018 | Apr 15, 20181天 1时 | $17430 | |
| programming mplab | programm an fm receiver chip to be able a radio to work mp lab software using c or c++ everything exxplained in files that will be sent | 18 | C 编程, Verilog / VHDL, 微控制器, C++编程, Arduino | Apr 13, 2018 | Apr 13, 2018已经结束 | $1698 | |
| Experts on Communication system, Digital Signal Processing, and Matlab needed 2 - 12/04/2018 18:48 EDT | Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks | 6 | 工程, 矩阵及数学软件, Verilog / VHDL, 电機工程, 通讯工程 | Apr 12, 2018 | Apr 12, 2018已经结束 | $243 | |
| Experts on Communication system, Digital Signal Processing, and Matlab needed | Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks | 3 | 工程, 矩阵及数学软件, Verilog / VHDL, 电機工程, 通讯工程 | Apr 12, 2018 | Apr 12, 2018已经结束 | $152 | |
| Mips, Verilog project | Small project on computer architecture | 20 | Verilog / VHDL | Apr 9, 2018 | Apr 9, 2018已经结束 | $165 | |
| State Machine and Timing Diagram for Embedded System | State Machine and Timing Diagram for Embedded System. More details to be provided. | 17 | Verilog / VHDL, 嵌入式软件 | Apr 9, 2018 | Apr 9, 2018已经结束 | $353 | |
| OS work ( Printing Service) | In this work, I need a coder who will design a programming solution to a variant of the boundedbuffer producer/multi-consumer problem using semaphores. The main goal of the task is to get familiar with the basic concepts of InterProcess Communication (IPC) and threads. Your implementation will be based on the following: shared memory, locks, semaphores and threads. More details will be prov... | 8 | C 编程, Java, Verilog / VHDL, C++编程, 编程 | Apr 8, 2018 | Apr 8, 2018已经结束 | $255 | |
| Systemverilog TCPIP model | Looking for a SystermVerilog TCPIP model which drives the MAC data to TCPIP DUT and analyze the data from DUT. Need some customization depending on the RTL. | 3 | Verilog / VHDL | Apr 6, 2018 | Apr 6, 2018已经结束 | $1451 | |
| NS3 simulation using c++ and ubunto NS3 simulator | NS3 simulation using c++ and ubunto NS3 simulator | 5 | C 编程, Linux, Verilog / VHDL, 软件构架, C++编程 | Apr 6, 2018 | Apr 6, 2018已经结束 | $2848 | |
| ns3 project c++ ubunto needed | i need this simulation for ns3 using c++ | 4 | C 编程, Linux, Verilog / VHDL, 软件构架, C++编程 | Apr 6, 2018 | Apr 6, 2018已经结束 | $1843 | |
| Simple SCADA WEB page | Web Page for monitoring data of sensor Login Security Historical reports Mobile COmpatibility Good Desing If you are interested you should write me a message saying you have experience in labview | 9 | PHP, 工程, Verilog / VHDL, 软件构架, LabVIEW | Apr 6, 2018 | Apr 6, 2018已经结束 | $1412 | |
| Vhdl coding for a small project | 1. Do some for loop in vhdl 2. Do some multiplication in vhdl 3. Add registers at input and output | 4 | Verilog / VHDL | Apr 4, 2018 | Apr 4, 2018已经结束 | $251 | |
| Serial Interface using Python | Design a serial interface using Python for communication with FPGA. | 5 | Python, Verilog / VHDL, 用户接口 / IA, 软件构架, FPGA | Apr 2, 2018 | Apr 2, 2018已经结束 | $250 | |
| Project for Usama S. | Hi Usama S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. | 7 | 电子, Verilog / VHDL, Research Writing, LabVIEW, , 学术写作 | Apr 2, 2018 | Apr 2, 2018已经结束 | $275 | |
| FPGA Programming Crypto Miner | I am looking for someone that can program or port an existing Windows or Linux mining program for AMD GPU's to a Xilinx Kintex-7 FPGA I will provide details and Github privately | 9 | C 编程, 电子, Verilog / VHDL, 微控制器, 电機工程 | Mar 30, 2018 | Mar 30, 2018已经结束 | $11178 | |
| parallel multiply simulation -vhdl | I need to create and minimize 2 small VHDL entities and their corresponding architectures. Can anyone help? I will provide with some files that are the basics to this, but still need to create 2 more. You need to be expert in VHDL language and have knowledge of computer architecture. | 13 | C 编程, 工程, Verilog / VHDL, 微控制器, FPGA | Mar 29, 2018 | Mar 29, 2018已经结束 | $259 | |
| Implementation of Leach protocol on tinyos | I have a Wireless sensor network project, I need to implement the leach protocol on a hardware that is compatible with tinyos. You must have: -Theorical background on WSN. -Experience on implementation on Tinyos. | 1 | C 编程, 无线, 工程, Verilog / VHDL, C++编程 | Mar 29, 2018 | Mar 29, 2018已经结束 | $149 | |
| JESD204B ADS54J20 vc707. - open to bidding | I have a project where i need to receive ads54j20 data with interface jesd204b on vc707. if your are interested please let me know and we can discuss details in a chat. | 6 | 电子, 矩阵及数学软件, Verilog / VHDL, 微控制器, FPGA | Mar 28, 2018 | Mar 28, 2018已经结束 | $5656 | |
| Build me iv.file | I have a project that deal with LABView app, or as it called iv. file. I need someone who is good at creating scheme and using LABView | 7 | Verilog / VHDL, 微控制器, 软件构架, LabVIEW, Arduino | Mar 28, 2018 | Mar 28, 2018已经结束 | $235 | |
| Implementation of Leach protocol on tinyos | I have a Wireless sensor network project, I need to implement the leach protocol on a hardware that is compatible with tinyos. You must have: -Theorical background on WSN. -Experience on implementation on Tinyos. | 3 | C 编程, 无线, 工程, Verilog / VHDL, C++编程 | Mar 28, 2018 | Mar 28, 2018已经结束 | $475 | |
| Absorption Chiller - open to bidding | I have some work in MATLAB i need this work to be finished asap (1-2 days lower bids would be preferred i have more work like this so i want serious freelancers Time wasters are not allowed to bid here NOTE: Milestone will be after seeing the full work | 4 | 矩阵及数学软件, Verilog / VHDL, 算法, 微控制器, FPGA | Mar 27, 2018 | Mar 27, 2018已经结束 | $395 | |
| RFID Read and Write using VHDL or Arduino | A code that will read data from RFID tag 1 using a RC522 Rfid reader and verify that to a stored value. Upon successful authentication, it will read data from RFID Tag 2. Then the program will generate a random number and store it in RFID tag 1 and also update the previous system stored value of tag 1. | 12 | Verilog / VHDL, Arduino | Mar 27, 2018 | Mar 27, 2018已经结束 | $196 | |
| Embedded Systems | use quartus compiler/simulator to design a [链接已删除，请登录查看] displays left 16 bits of the result in hexadecimal format...................................................... | 6 | C 编程, Verilog / VHDL, 微控制器, C++编程, FPGA | Mar 26, 2018 | Mar 26, 2018已经结束 | $251 |
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