Verilog / VHDL Jobs

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Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. 雇佣Verilog / VHDL Designers

10 搜到的工作，价格货币为 HKD

Dice game on Quartus II 6 天 left

I have a project coming up ‪in less than 12 hours‬. I would appreciate if you can help me individually in doing the project in anyway at a deal that shall satisfy your effort. please take a look at the instructions and let me know if you can help: You will use the Altera DE2-115 board (Side note: you only need to design the software and I will install it to the board myself), Quartus II software ...

C 编程 C++编程电子微控制器 Verilog / VHDL

$2793 (Avg Bid)

$2793 平均报价

6 个竞标

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Simple CheckSum Program 6 天 left

Create an Adler-32 offload engine. As part of a larger system a required will be a provided resource to compute the Adler-32 checksum on data being sent to you a byte at a time.

C 编程数字设计徽标设计 Verilog / VHDL

$447 (Avg Bid)

$447 平均报价

9 个竞标

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1ns Bin Size Histogrammer, FPGA + ADC 6 天 left

I have a digital input measurement signal, 0 ~ 1.1V level. Each pulse is an event, that has a level HIGH width from 5ns to 10ns, and the minimum time between every 2 pulses' rising edges is 20ns. I need a system to histogram the time between all adjacent pulses' rising edges, that each bin of the histogram is 1ns wide. For example, starting from t=0, if the input signal has rising edge...

电機工程电子 FPGA Verilog / VHDL

$7320 (Avg Bid)

$7320 平均报价

3 个竞标

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wireless body area sensor node protocol 6 天 left

My project require someone knowledgable in the area of wsn. The main Idea would be enhancing a currently existing routing protocol in wireless sensor nodes, the code can be done in any language, I prefer Matlab and or c++ using omnet++ simulator

C 编程 C++编程电機工程矩阵及数学软件 Verilog / VHDL

$9203 (Avg Bid)

$9203 平均报价

12 个竞标

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z7010 DMA Controller Red pitaya 3 天 left

Hello i am working on red pitaya board which has z7010, and i need help with DMA controller. I have troubles managing data transfer between AXI Stream IP and DDR memory. The project is setuped completely the application is also written. but its not working as supposed to. The thing i need from freelancer is that you need to debug the design an c code, i ame sure minute changes are required. onl...

数字设计 FPGA Verilog / VHDL

$203 (Avg Bid)

$203 平均报价

1 个竞标

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VLSI work.. 2 天 left

Design and analyze different MOS combinational logic circuits

电路设计电機工程电子工程 Verilog / VHDL

$235 (Avg Bid)

$235 平均报价

6 个竞标

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Looking for Vivado HLS expert 1 天 left

Need to know the knowledge of Blockchain algorithm and FPGA programming(VHDL/Verilog), C++ programming. Will discuss more via interview.

算法 Blockchain C++编程 FPGA Verilog / VHDL

$7916 (Avg Bid)

$7916 平均报价

14 个竞标

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embedded system 1 天 left

need a free lancer trainer for embedded system in AVR , ARM , PIC AND IOT'S for training purpose

C 编程电機工程电子微控制器 Verilog / VHDL

$146 (Avg Bid)

$146 平均报价

6 个竞标

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embedded system project 23 小时 left

interface a blood pressure sensor with microcontroller

Arduino 电機工程电子微控制器 Verilog / VHDL

$989 (Avg Bid)

$989 平均报价

19 个竞标

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Nand flash rom refreshing 13 小时 left

Need some ONFI experts to help in accessing rom via Xilinx ISE design Suite or Vivado. I have my own rom, wanting to change the default rom.

计算机安全网络安全 Verilog / VHDL 网络安全

$38644 (Avg Bid)

$38644 平均报价

7 个竞标

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