Verilog / VHDL jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. 雇佣Verilog / VHDL Designers

筛选

我最近的搜索
筛选:
预算
项技能
语言
    工作状态
    7 找到的工作,价格在 HKD

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible light communication (VLC) system. The projects in...

    $35158 (Avg Bid)
    $35158 平均报价
    20 竞标

    I work for a company that builds Air Cooled Heat Exchangers. We pressure test all of our units before they leave the plant to ensure they hold pressure without any leaks. To improve safety, we are going to a fully automated test system, which is to be controlled by a DAQ system using a Laptop. I am looking for someone to write me two separate (but very similar) LabView programs for both of the te...

    $29138 (Avg Bid)
    $29138 平均报价
    28 竞标

    Build a robot connecting circuits and programming

    $8030 (Avg Bid)
    $8030 平均报价
    32 竞标
    H.264/H.265 decoder 2 日 left
    已验证

    The project is to design a video decoder for H.264/265 in ASIC design Performance requirement 1080p30 x 8 channels

    $36147 (Avg Bid)
    $36147 平均报价
    11 竞标

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    $3061 (Avg Bid)
    $3061 平均报价
    3 竞标
    DMA controller for AXI4 1 日 left
    已验证

    This project is to design a DMA engine for the AMBA4 system. The engine has one 512b AXI4 master and one 32b AXI4-lite configuration interface. The engine supports following DMA mode: • 1D mode: Single continuous block • 2D mode: multiple continuous blocks equally spaced. • 3D mode: multiple 2D block equally spaced. • Interleaving mode: read multiple blocks and send out interl...

    $3823 (Avg Bid)
    $3823 平均报价
    11 竞标

    Design and simulate a typical RF Telecommunication receiver system IN SIMULINK/MATLAB/LABVIEW

    $1217 (Avg Bid)
    $1217 平均报价
    32 竞标