Verilog / VHDL 工作与竞赛

Verilog是一种用于半导体和电子设计领域的描述语言,也常用于模拟和模数混合电路中。VHDL则是一种用于电子设计自动化和集成电路的硬件描述语言。如果您的业务涉及Verilog / VHDL,您可以雇佣一些自由职业者完成部分作业。现在就发布您的Verilog/VHDL项目需求,与中意的自由职业者取得联系吧。
注册并开始赚钱
注册来开始赚钱。 您是a Verilog / VHDL Designer吗?您可以从这些工作中获得报酬!

浏览Freelancer上的工作

项目/竞赛 描述 竞标数/参赛作品数 技能 已开始 结束 价格(HKD)
VHDL to Verilog Translation I have .vhdl files for an implementation of google chrome's 'dino run' which appears when the user has no wifi connection. However, I would like to have the same functionality with Verilog description language. 5 Verilog / VHDL Dec 10, 2017 今天6天 21时 $929
FPGA developer Looking for a developer to code a specific simple algorithm which is based around SHA3 (Keccak) into iCE40UltraPlus FPGA using the standard low-cost breakout board from Lattice: iCE40UP5K-B-EVN. In general there will be incoming data block over a serial channel, encrypting, and sending it back to the same serial channel. More details will be given in personal communication. I am not sure about ... 11 电子, Verilog / VHDL, FPGA Dec 9, 2017 Dec 9, 20175天 10时 $251
simulation/ VHDL Expert Needed -- Urgent job -- b I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 6 工程, 电子, Verilog / VHDL, 电機工程, FPGA Dec 9, 2017 Dec 9, 20175天 2时 $410
System verilog Verification Project Plz contact me. I have other code for it as well. You will just need to restructure the code and it should be good enough. 11 工程, 电子, Verilog / VHDL, 电機工程, FPGA Dec 9, 2017 Dec 9, 20175天 2时 $207
simulation/ VHDL Expert Needed -- Urgent job -- 3 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 工程, 电子, Verilog / VHDL, 电機工程 Dec 9, 2017 Dec 9, 20175天 2时 $334
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 工程, 电子, Verilog / VHDL, 电機工程 Dec 9, 2017 Dec 9, 20175天 2时 $275
simulation/ VHDL Expert Needed -- Urgent job -- 2 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 工程, 电子, Verilog / VHDL, 电機工程 Dec 9, 2017 Dec 9, 20175天 2时 $275
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 0 工程, 电子, Verilog / VHDL, 电機工程, FPGA Dec 9, 2017 Dec 9, 20175天 2时 -
simulation/ VHDL Expert Needed -- 2 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 4 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 9, 2017 Dec 9, 20175天 1时 $264
simulation/ VHDL Expert Needed I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 9, 2017 Dec 9, 20175天 1时 $299
Electronics Engineer/Tutor Hi, I am looking for a Electronics Engineer/Tutor who can tutor me some important concepts of the Engineering Design. I am looking for someone who has background in Electronics and Digital Logic Design. Happy Bidding! 18 工程, 电子, Verilog / VHDL, 电機工程 Dec 8, 2017 Dec 8, 20174天 23时 $94
DDR SD ram controller DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero 9 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Dec 8, 2017 Dec 8, 20174天 $3430
FPGA Implementation of FIR filter 1. FIR design and simultion in Matlab. 2. Implement in FPGA(Xilinx Virtex-6 LX240T) and inter-connect with other logic blocks. 3. define registers for FIR filter and gain setting such that user can download filter co-efficients and gain settings through software to FPGA. 24 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Dec 7, 2017 Dec 7, 20173天 22时 $6115
Digital Logic Circuit using Logisim Hello, I am looking to build a circuit in Logisim that requires digital logic expertise. Project description will be provided upon contact. Computer science backgrounds, circuit design, and digital logic expertise required (preferably using Logisim). 22 工程, 电子, Verilog / VHDL, 电機工程, 数字设计 Dec 6, 2017 Dec 6, 20172天 14时 $672
need help with missile command game on de2-115 does anyone experienced with verilog have de2-115 I need help displaying a sprite on the screen. I have all the files. 4 Verilog / VHDL Dec 5, 2017 Dec 5, 20171天 12时 $992
micro controller need somebody good in micro controller and has ever coded using vhdl 18 C 编程, Verilog / VHDL, 微控制器, 电機工程, FPGA Dec 5, 2017 Dec 5, 20171天 9时 $1359
Expert in Xilinx (VHDL-BASED) An efficient Glitch power reduction using sequential clock gating in VLSI circuits 8 Verilog / VHDL Dec 5, 2017 Dec 5, 20171天 1时 $1265
Project for SqUa11 -- 2 3x3 Systolic array matrix using rom and ram 2 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, Dec 4, 2017 Dec 4, 20173天 22时 $94
Embedded systems Develop a minimal system that contains a PC, a microprocessor board, and an FPGA board. With this system, a PC application allows a user to “awaken” (or “start up”) the FPGA board through the microprocessor board. Once (and only after) the FPGA board is awakened, it waits for a push button action. After the button is pushed, it sends an 8-bit value in bit-serial to the... 9 电子, Verilog / VHDL, 微控制器, 软件构架, Arduino Dec 4, 2017 Dec 4, 201717时 19分 $328
Implementation of 32-bit MIPS Processor I need someone who knows MIPS Assembly Language and knows how to use the LogicWorks software to design a Single-cycle processor (see Figure 1 in attached document) and a Five-stage pipelined processor (see Figure 2 in attached document). Please keep all bids within the budget, otherwise you will not be selected for the project. 7 C 编程, Verilog / VHDL, 软件构架, 汇编, x86/x64 汇编 Dec 4, 2017 Dec 4, 201714时 12分 $914
Write an article about UVM (universal verification methodology) Dear ASIC Verification Experts, I am looking for ghost writer who is from ASIC verification background. I want a unique article which tries to explain why we need to use UVM. The title of the article will be similar as this. "If SystemVerilog is so good, why do we need the UVM? " The article needed to be original and meaningful content. Please bid with your experience in ASIC ver... 26 Verilog / VHDL, 技术写作 Dec 4, 2017 Dec 4, 20176时 16分 $765
putty language i need someone who can do putty and verilog 7 工程, Verilog / VHDL, 电機工程, 汇编 Dec 4, 2017 Dec 4, 2017结束 $867
Verilog Work I need some work done in verilog using Quartus 2 version 13 12 Verilog / VHDL Dec 3, 2017 Dec 3, 2017已经结束 $1132
putty coding language need an electrical engineer or computer engineer with background in putty language coding 3 Verilog / VHDL, 电機工程, 编程, 编程 Dec 3, 2017 Dec 3, 2017已经结束 $219
Need a Cadence design to design a amplifier circuit. Need a Cadence design to design a amplifier circuit. details will be share in chat box. 21 工程, 电子, Verilog / VHDL, 电機工程, 电路设计 Dec 3, 2017 Dec 3, 2017已经结束 $194
Design of MIPS Datapath components Using Logisim Course: Computer Organization and Architecture Project: Design of MIPS Datapath components Using Logisim Objectives After completing this project you will: · Design a 32x 32 bit register file · Design a 32 bit arithmetic and logic unit (ALU) Register File The register file consists of 32 x 32-bit registers and has the following interface as shown in Figure 1: _ BusA and BusB... 10 工程, 电子, Verilog / VHDL, 电路设计, FPGA Dec 2, 2017 Dec 2, 2017已经结束 $351
MATLAB code- a bit-serial CORDIC computer in Verilog MATLAB code a bit-serial CORDIC computer in Verilog to compute the sine and cosine of an angle θ. I will share the additional details later 15 矩阵及数学软件, Verilog / VHDL Dec 2, 2017 Dec 2, 2017已经结束 $484
Digital Design with Logic Devices It is a Project on Digital Design with Programmable Logic Devices. I will provide details later. 10 Verilog / VHDL Dec 1, 2017 Dec 1, 2017已经结束 $406
pls help ac homewokr :'( i need log synchronous sequential circuit that solves a 64x64 maze using the right wall follower algorithm. how much???? u have 3 hours 8 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 1, 2017 Dec 1, 2017已经结束 $649
Project for Gabriel G. Hi Gabriel! I'm working on my capsim simulation final and I got myself into a lot of debt and don't know how to fix it . I need a 70% on this and was wondering if you'd be able to help. Im currently on the 3rd round of 4. Would you be able to help me out? You were suggested by a classmate and was wondering if you'd be able to help me even though I already am on round 3. Thank... 2 项目管理, 电话销售, Excel, 矩阵及数学软件, Verilog / VHDL, Dec 1, 2017 Dec 1, 201713时 10分 $1148
design and implementation of a MIPS CPU with Multi cycle Data path design and implementation of a MIPS CPU with Multi cycle Data path using the VHDL language 14 C 编程, Verilog / VHDL, C++编程, 汇编, FPGA Nov 30, 2017 Nov 30, 2017已经结束 $1226
bubble level project the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board. In the video attached in the .zip, the operation of the project 8 Verilog / VHDL, FPGA Nov 29, 2017 Nov 29, 2017已经结束 $648
VHDL code for Pipe lined MIPS-RISC (5 stage) processor.(Code for Un-pipelined will be given) I need you to do pipelining for the MIPS-RISC (5 stage) Processor. I will give you the MIPS processor code, all you need to do is pipelining. I will upload the file once go through it. If you are interested, I will send you the code and question for which code has written.” Deadline is " Dec-03-2017 " 12 C 编程, 工程, Verilog / VHDL, FPGA, 并行处理 Nov 29, 2017 Nov 29, 2017已经结束 $1343
logic analyiser and waveform viewer The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports one analog channel and one digital channel, with a single-level triggering. Only 8 bits of precision will be used for the analog channel. •Phase 1: Develop a minimal system that contains a PC, a microproce... 6 电子, Verilog / VHDL, 微控制器, 软件构架, Arduino Nov 27, 2017 Nov 27, 2017已经结束 $2514
interface hardware module with amber processor -- 2 - 27/11/2017 11:51 EST to implement an interface hardware module with amber processor 2 Verilog / VHDL Nov 27, 2017 Nov 27, 2017已经结束 $1648
Network traffic processing using two FPGAs I want to get throughput and latency results of network traffic(Ethernet packets processing) using two FPGAs, while i have throughput and latency results of using one FPGA, so i want to compare both these results. The results of using two FPGA chips should be better than using one FPGA. 6 工程, Verilog / VHDL, 电機工程, 网络管理, FPGA Nov 26, 2017 Nov 26, 2017已经结束 $5271
C++ based project - open to bidding cpp dependencies sorting out, we will provide you the structured file and the source code and you have to compile and run after sorting mugs from that 16 电子, Verilog / VHDL, C++编程, Arduino, 实时操作系统 Nov 25, 2017 Nov 25, 2017已经结束 $843
Design and test a VHDL model for the instruction cache of a speculative out of order VLIW processor. Design and test a VHDL model for the instruction cache of a speculative out-of-order VLIW processor. Your VHDL code should have the following: - PC register updated on falling_edge of the clk to one of the following values: PC + VLIW_INST_SIZE, branch_target_PC, or EXCEPTION_ROUTINE_PC. PC register should be initialized to 1000 Hex when reset is active. Assume that the project ISA requires EXCE... 3 Verilog / VHDL Nov 25, 2017 Nov 25, 2017已经结束 $2819
System verilog - open to bidding I need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. Thanks 10 C 编程, Verilog / VHDL, C# 编程, C++编程, FPGA Nov 23, 2017 Nov 23, 2017已经结束 $83
interface hardware module with amber processor to implement an interface hardware module with amber processor 2 Verilog / VHDL Nov 23, 2017 Nov 23, 2017已经结束 $234
single cycle 32bit mips verilog code -- 2 i need verilog code for 32bit mips single cycle it must contain instructions LW, SW, AND, ADD, ADDI, SUB, SLT, SLTI,b,BEQ, BNE, J, JAL and JR. and write a test-bench and stimulate and get the output waveform synthesis the code and submit to me 10 C 编程, Verilog / VHDL, C++编程, 汇编, FPGA Nov 23, 2017 Nov 23, 2017已经结束 $78
write a simple code for sample testing k Please check new schematic diagram in attached. And IC datasheet. Please write a simple code for sample testing 9 电子, Verilog / VHDL, 微控制器, 电機工程, 电路设计 Nov 22, 2017 Nov 22, 2017已经结束 $790
Using VHDL Implement a simple MIPS-2 RISC Processor It is a Project Using VHDL Implement a simple MIPS-2 RISC Processor. i will give the details later. 4 Verilog / VHDL, 电機工程 Nov 22, 2017 Nov 22, 2017已经结束 $796
System Verliog task available I need someone who can do task on system verilog. Deadline is 2 days. I want someone who can start now. More details will be provided to interested freelancer 8 工程, 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Nov 22, 2017 Nov 22, 2017已经结束 $184
Computer Design and ProtoTyping build a 32 bit architecture CPU, the CPU include the Register File, ALU, Control Unit, Instruction Register, Data Memory, PC Register, Shift logic unit, Conditional Logic Unit, and a 3-level cache read and write memory for the Data memory. The units need to be built in Verilog HDL then represented as a symbol on a schematic diagram and connected together using wires. Accompanied with each unit s... 8 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Nov 22, 2017 Nov 22, 2017已经结束 $1382
VHDL coding needed to be done by expert!! VHDL coding needed to be done by expert!! $30 CAD pay 8 工程, 电子, Verilog / VHDL, 电機工程, FPGA Nov 22, 2017 Nov 22, 2017已经结束 $172
UVM verification of memory controller - open to bidding Need someone to verify a memory controller using UVM environment. CAN bus is used as a memory cycle initiator and write/read burst transactions need to be verified. 5 Perl, Verilog / VHDL, shell脚本, FPGA, Very-large-scale integration (VLSI) Nov 21, 2017 Nov 21, 2017已经结束 $2928
SMC Interface and SPI Slave Logic for CPLD Project 1) Implement high-speed 8-bit bus for MCU (ATSAM3U) to connect to Altera CPLD (5M160ZM68C5N) 2) Implement SPI Mode-0 SPI Slave in CPLD logic 3) Implement Dual SPI Slave mode in CPLD logic 4) Implement QUAD SPI Slave mode in CPLD logic 5) Implement general purpose I/O (8-bit) Port B in CPLD logic 6) Implement JTAG Host shift logic in CPLD logic 7 C 编程, 电子, Verilog / VHDL, 微控制器, FPGA Nov 21, 2017 Nov 21, 2017已经结束 $219
Video transmission system and USB emulator Project for huge experienced engineers. Result: Altium project and firmware. Details of the project in the attachment. 4 电子, Verilog / VHDL, 印制板布局, FPGA Nov 20, 2017 Nov 20, 2017已经结束 $11002
Differential Scan-attack and countermeasures on AES crypto-algorithm Hi, I wanted to implement research work on the AES(Advnaced Encryption Standard) algorithm and differential scan attack on the same to retriever secret key. In addition, the prevention mechanism against such attack has to be developed. Coding and simulation in verilog(Xilinix-ISE/Modelsim) will be fine. Also, requires documents for the implementation (step-by-step procedure), block diagram ... 8 工程, Verilog / VHDL, 电機工程, 密码学, FPGA Nov 19, 2017 Nov 19, 2017已经结束 $7380
Showing 1 to 50 of 165 entries
« 1 2 3 4 »