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conversion using specific logic on verilog files

Input and output files are given. Using a specific logic, input file needs to be converted to output file as attached. Algo will be provided. Inbox for more details!

技能: Python

查看更多: parsing files logic

About the Employer:
( 13 reviews ) Mumbai, India

项目ID: #12018320

2名威客为此工作的平均竞标价是₹2403

cracken

Hi, I am competitive to this kind of task, can take good care of this project. In fact, I already done related to this job before. Let me know the best of your time so we can discuss further based on your requirements 更多

₹3055 INR 在0天内
(9条评论)
4.4
leonidmanyshinn

Good morning. I am concerning your project. I have faced the same question recently and have found a good specialist. It occurred not so easy to do. Try to contact Sergey Zlobin sergey_zlobin77(@mail.ru). They work qu 更多

₹1300 INR 在10天内
(0条评论)
0.0
Dhanasekarsr

Hi. This will be a needed amount to done this task. kindly let me know about the task. Waiting for your reply

₹1750 INR 在2天内
(0条评论)
0.0