Building a VGA Display Driver, I/O Driver, and Memory Mapping!

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Specifics in attached .pdf's

Supporting source code will be supplied.

For someone with SystemVerilog/VHDL/FPGA/ASM experience this shouldn't take more than a few hours.

Must be completed by 4/26/2016 - Willing to negotiate Bonus if completed sooner.

FPGA Verilog / VHDL x86/x64 汇编

项目ID: #10272155

关于项目

2个方案 远程项目 活跃的7 年前

有2名威客正在参与此工作的竞标,均价$211/小时

ahmedmohamed85

A proposal has not yet been provided

$222 USD 在2天内
(403条评论)
7.8
islamrefaat

I have more than seven-year experience in digital design and HDL. I already did a similar project before and have some Verilog codes that may help in your project. I can finish this project over the weekend if you wish

$200 USD 在2天内
(2条评论)
2.5