Building a VGA Display Driver, I/O Driver, and Memory Mapping!
$30-250 USD
货到付款
Specifics in attached .pdf's
Supporting source code will be supplied.
For someone with SystemVerilog/VHDL/FPGA/ASM experience this shouldn't take more than a few hours.
Must be completed by 4/26/2016 - Willing to negotiate Bonus if completed sooner.
项目ID: #10272155
关于项目
有2名威客正在参与此工作的竞标,均价$211/小时
I have more than seven-year experience in digital design and HDL. I already did a similar project before and have some Verilog codes that may help in your project. I can finish this project over the weekend if you wish