I have long experience with FPGA and VHDL . I work with both intel and Xilinx FPGAs , SoC
and SOPC. I use Quartus II and Vivado IDEs accordingly.
I test timing compliance through timing analysis . I deliver tested , neat and
well-commented code that can be reused or modified for future development.
More to be discussed once you contact me .
BR,
M.T.