FPGA developer

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you! Verilog and Digital Design - 4+ years

I would recommend the following approach. Divide the project into two parts, 1> The first part consisting of scoping out the project, defining the architecture and creating a schedule estimate.. A max limit of 10 hrs can be assigned for this activity. 2> Based on the architecture determined in Part 1 initiate the actual design/implementation and verification of the Algorithm. In case the above plan looks feasible please initiate a chat and we can discuss further. About Me. ========== I have worked for ~20 years in ASIC Design before founding my own ASIC Design startup Dyumnin Technologies I have worked on cryptography and communication technologies... More details can be found on my profile page. Regards Vijay

I have extensive knowledge in digital design and VHDL. I mainly have worked on Xilinx FPGAs, Lattice semiconductors' products are no stranger.

I am a professional design engineer in Germany with MSc too. I develop FPGA hardware and software design for industrial applications with Cyclone V and MAX10 devices. I developed a custom serial channel over LVDS too. I also work part-time on freelancer. I am currently hired for an altera CPLD custom memory controller design. I can design a low-latency and parallel architecture for SHA3. I can buy the ice dev kit too and will work closely with you to deliver the results in short time and hence saving you time and money. If you meant SPI from serial interface then i guess lattice already have an SPI core available that i will use. I have basic knowledge of hashing and security functions. I can implement SHA3 which basically involves adders and xor logic. A highly parallel design is possible if inter sample dependency is less between memory accesses. Lets have a chat and discuss the detail architecture for serial communication and hashing functions.

Dear, We will write code in verilog for desired functionality. Behavioral modeling will be used for this project. Deliverable will be Verilog code, test bench and simulation files. Regards,

hi i would like to know more about the project, bid salary is not definitive and we can talk about that.

We are an engineering small startup in Brazil. We have lots of experiente in FPGAs, recently we achieved Xilinx Alliance Partnership (which only helps in this case as a mean to support our claim). Regards, Ricardo