RS-FEC 198,194 verilog code

已完成 已发布的 4 年前 货到付款
已完成 货到付款

VLSI design for Reed Solomon FEC for 198,194 including documentation and explanation.

Verilog files and simple testbench to prove the design.

ASIC

电气工程 电子 工程 FPGA Verilog / VHDL

项目ID: #20012622

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8个方案 远程项目 活跃的4 年前

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hzarsuela

Hi! I believe I understand what you need. I have done several Verilog/VHDL design projects which are either implemented in FPGA (Xilinx and Lattice) or ASIC for the past 10 years. In fact, I already implemented the 更多

$100 USD 在9天内
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2.0

有8名威客正在参与此工作的竞标,均价$110/小时

hsh564cf84accd96

Hi my Professional Aim is: ( Services then Solutions then Satisfactions) I hope you are good. As an experience in this field from last 5 years i am sure i can do it perfectly with in a time a 更多

$30 USD 在3天内
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thasleemkamila

I have well experienced in doing such kind of jobs........................................................................................................................................................................ 更多

$50 USD 在3天内
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VirtualBrainInc

Hello! I have briefly read the description on fec-verilog-code development project, and I can deliver as per the requirements however I need us to discuss for more clarity on the details, deadline and budget as 更多

$100 USD 在3天内
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4.5
iZoneFreelancer

Hi, I have worked on Verilog, VHDL, System Verilog and have developed many complex IPs for FPGA and ASICs. I can develop this verilog code for you. Let me know whether you are looking for an encoder only. Also shar 更多

$250 USD 在7天内
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phalakegirish7

Hello sir, i am girish Phalake, FPGA design engineer with better industry experience, i am very good at paper design and also good in english Thank you!

$166 USD 在3天内
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abdelharizchaou

I have well experienced in the following topics.. Electronic circuits,Digital electronics Signals and system,Digital signal processing Digital image processing,Verilog/VHD 更多

$30 USD 在10天内
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