Piccolo cipher implementation in VHDL/Cryptography

已完成 已发布的 5 年前 货到付款
已完成 货到付款

Hi there!

I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found in the pages between 342 to 355.

The code has already been developed and I'm getting the proper results as well. But I want to build a clock based design so that I can perform power analysis on it. Need the code properly working in two days.

Note: Clock based implementation on existing design

Language used : VHDL

电气工程 工程 FPGA Verilog / VHDL

项目ID: #17513156

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2个方案 远程项目 活跃的5 年前

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profvipabutaleb

I'm electronics and communications engineering 10+ years of experience FPGA - Verilog - VHDL - Spartan - ZYNQ - Xilinix

€24 EUR 在1天内
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