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R-type Single cycle MIPS with Structural Verilog2

* DEADLINE: SATURDAY 11 PM **

You will design a MIPS processor but only supporting the R-type instructions in

the MIPS Green Sheet. (I will add this on files) Only the register block in your design will be behavioral

but other than that, all your design must be structural.

Your MIPS will take a 32-bit instruction as input, so there will be no instruction

memory. Also you will not implement lw/sw instructions therefore there will be no

data memory.

The output of your block will be the output of ALU, but you also have to write the

result to the $rd register as R-type instructions require.

Write a structural Verilog on Altera Quartus II tool to implement a 32-bit R-type

MIPS. Only structural Verilog is allowed, dataflow and behavioral Verilog is not

allowed except for the register module. This means you cannot use assign, ifelse,

always, ?: and etc.

Use hierarchy in your project. For instance, you can design a Register module and

use it as an instance in your datapath.

You will not support floating point instructions, I-type instructions or J-type

instructions. Also you will not implement jr and slt. All other R-type instructions

(including sltu) in the MIPS Green Sheet will be implemented.

Hint: Start with drawing schematic on paper for each module. Do not hesitate to write 32 lines of logic expressions for each bit of one or two 32-bit numbers whenever required.

You have to simulate all instructions by yourself via Modelsim and put the results in your report as well as to your zip folder including all your project files to submit.

Rules:

1. Behavioral or Dataflow Verilog are not allowed.

2. Not compiling or not simulating solutions not allowed.

3. You have to use Quartus II tool referred in Moodle.

4. Each day of late submission will get 25 point loss.

5. Write at least Register Block and Alu Control as modules.

6. The name of your top module should be alu32.

7. You should desing a 32 bit ALU in this project.

The details of the 32 bit ALU:

Only structural Verilog is allowed, dataflow and behavioral Verilog is not allowed.

This means you cannot use assign, if-else, always, ?: and etc.

The primitive gates that you can use in structural Verilog are listed below ( i will add them on the files)

The ALU will get two 32-bit numbers A and B, and a 3-bit S (select) signal as inputs

and a 32-bit R signal as output. The ALU perform the following operations ( i will add them on the files)

I will add a template on files.

Useful links:

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技能: 汇编, 电子, 工程, FPGA, Verilog / VHDL

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( 1条评论 ) kocaeli, Turkey

项目ID: #18312221

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PredatorX374

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hungfreelancer

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