Digital down converter and Digital Up converter

$250-750 USD

已取消

已发布

超过 6 年前

$250-750 USD

货到付款

Digital down converter , Digital Up converter VHDL & Matlab . DDC: 1- Fsample : 16 bit x 400 MSPS Max. 2- Bandwidth : programmable from 100Khz to 20Mhz. 3- IF Tuner : programmable from DC to 100Mhz , resolution 0.5Hz . 4- DDC decimation Range : 8 to 4096 . 5- CFIR : programmable 20 taps( 18 bit coefficient ) . 6- PFIR : programmable 80 tabs ( 18 bit coefficient ). 7- Manual gain control and overflow indicator. DUC: 1- Fsample : 16 bit , 400 MSPS Max . 2- SFDR >115dB. 3- Tuning resolution : 0.0582 Hz. 4- Interpolation range : Programmable 2 to 32768 . 5- CFIR : programmable 20 tabs x 18bit. 6- PFIR : Programmable 80 tab x 18bit . 7- Bypass interpolation filter On/OFF programmable . 8- Gain control up to 60dB . 9- Overflow Indicator .

Digital Design

FPGA

Matlab and Mathematica

Telecommunications Engineering

Verilog / VHDL

项目 ID: 14723930

关于此项目

9提案

远程项目

活跃7 年前

想赚点钱吗？

电子邮箱地址

在Freelancer上竞价的好处

设定您的预算和时间范围

为您的工作获得报酬

简要概述您的提案

免费注册和竞标工作

9威客以平均价$598 USD来参与此工作竞价

@seshupower

Hi, I am a post graduate power electronics engineer and having very good experience in product design and development. I am excellent in embedded design & programming using pic, dspic controllers and MATLAB codding for Power projects, Boot loaders, Bluetooth & GPS designs,CAN communication, EEprom. UART , Protocols for networking, wi-Fi routers,OBD diagnosis with CAN bus protocols

$777 USD 在20天之内

4.9

(34条评论)

6.2

@luvtomar

I'm a recent Bachelor of Electrical Engineering from Carleton University. I've designed Digital Up & Down Converters in the past with MATLAB and VHDL and am confident I can do it again. Relevant Skills and Experience VHDL, MATLAB, Digital Integrated Electronics Proposed Milestones $277 USD - complete VHDL and MATLAB code

$277 USD 在5天之内

4.9

(16条评论)

4.5

@Elecguru011

Hi , I am expert FPGA design engineer with major projects done for DSP applications Relevant Skills and Experience VHDL/Verilog , C/C++ , SOC based Design , Altera / Xilinx Proposed Milestones $100 USD - Project Requirements $600 USD - Working Code $21 USD - Testing and Debugging What is your target device Altera or Xilinx

$721 USD 在30天之内