I'll create VIP for AXI with master and slave modes in constrained verification random environment. If UVM is ok, i'll base that testbenc on UVM.
Relevant Skills and Experience
Expert System verilog knowledege, many years of verification experience
Proposed Milestones
₹3000 INR - Create all components of testbench including drivers, monitors, scoreboard, environment
₹2000 INR - Add sequences and create basic tests, to make sure master and slave are working correctly
₹2777 INR - Add random sequences, create more tests, also coverage and assertions will be added.
Question: Is it ok to base this testbench on UVM SV?