FIR Filter Reference Design in Verilog
$240-2000 HKD
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We are looking for a FIR filter design in Verilog with the following requirements:
- 16-bit input, 16-bit fixed coefficient
- 39-bit output
- 256 taps
Please provide 2 implementations:
1. serial implementation using 1 multiplier
2. partial parallel implementation with 4 multiplers
项目ID： #16227583
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Hi, my name is Zeeshan. I would love the opportunity to assist you in designing FIR filter in Verlog. I have read your requirements and can design a good filter in Verilog. I have completed BS Electrical Engineering a 更多
有4名威客正在参与此工作的竞标，均价$1594/小时
Dear sir I have more than 10 years experience in digital design using verilog I have done many implementations of FIR filter and I can fullfill all the requirement Best regards
Hello! Please check my profile and reviews to know a bit about me and my work. It would be great if I could help you out with the same. Thank you!
