5-Stage , 8 Bit pipelined Processor

已完成 已发布的 5 年前 货到付款

$30-250 CAD

货到付款

已完成 货到付款

Hi , we need help debugging and implementing stalls and data forwarding for a 5 stage pipelined [login to view URL] processor uses RISC-like instruction set. The processor has four internal registers: R0, R1, R2, and R3. Each register is 1-byte. The address space of instruction memory and data memory is 256, and the processor uses little-endian byte ordering. The length of all instructions is the same and is 2-byte. There are total 16 instructions for the processor.

I am done with most of the coding but processor is not giving the output, we have very limited time of 24 hours for this

Computer Science Electronic Design FPGA Verilog / VHDL

项目ID： #18332176

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ducdctoandh的简历照片
ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a 更多

$250 CAD 在0天内
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SqUa11的简历照片
SqUa11

Hello My name is Mohamed. I have 5 years experience in Digital Design and VHDL. I checked your project description about debugging your code for 5 stage RISC and I can help you. COntact me for more details. Regar 更多

$250CAD 在1天里
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ENOESYSTEMS的简历照片
ENOESYSTEMS

I can help with the debugging process, Kindly share the Instruction set , RTL and Test bench files. You don't need to pay anything in advance. You said you are in a tight deadline, So first will work on the simulation 更多

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