Yassen M.

My name is Yassen Maged, I'm a Jr. FPGA Designer. Studied Electronics and Communication Engineering at the University. I work with a passion for problem-solving and a knack for innovative thinking. Skilled in VHDL and Verilog, with hands-on experience in designing, coding, and testing FPGA systems. Committed to delivering high-quality results within strict deadlines. Always eager to learn and adapt to new technologies and challenges. I look forward to bringing my expertise to exciting new projects.