Write some code in VHDL
₹600-1500 INR
货到付款
Create a VHDL file of a Full Adder using only gate-level description.
Only those bid who can complete it with 5 hours from now.
项目ID: #13196858
关于项目
有14名威客正在参与此工作的竞标,均价₹3011/小时
Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TS 更多
Hello, I am an electronics engineer having experience of VHDL based system design for more than 5 years. I can delver this code within 1 hour.
Hi, I am Prasad,interested to take up the your work. I will not take any advanced mile stones. If you are interested please share the details. Thanks and regards, Prasad.M
published 2 research papers on IEEE. Providing service in academic, project, training, coaching in VHDL, VerilogHDL since 2009. Experience of completing projects on Quartus, Xilinx, Modelsim, NIOS II. Worked on re 更多
Hi I am Computer Engineer Yes, I can do this approx in 1 hour. Give me chance to do your work. Thanks....
I am a Software Engineer. I will do your work very efficiently and on time. I've much experience in these type of work and I have already done many projects of this type. I can send you those work if you are interes 更多
Hello, hope you are enjoying good health. I am an embedded system designer and have hands on working experience with FPGA,s. i have worked in both VHDL and Verilog. I can complete and deliver this project with in 30min 更多
i have already worked on the full adder project and its test bench and am ready to give it to you whenever necessary.
Hi, I can provide you this in less than one hour. I have more than 4 years of experience in respective field.
Hello ! I'm ready to do your project, with high quality and very good result. I'm VHDL Desinger in my work. My salutations