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$15 USD / 小时
BANGLADESH的国旗
gaibandha, bangladesh
$15 USD / 小时
目前这里是3:04 下午
八月 2, 2017已加入
8 推荐

Md Rubel S.

@rubelsarkar161

 5.0 (8条评论)
4.5
4.5
75%
75%
$15 USD / 小时
BANGLADESH的国旗
gaibandha, bangladesh
$15 USD / 小时
100%
工作已完成
100%
在预算内
100%
按时
7%
重复雇用率

Electronics & IC Mask Layout Design Engineer

I am a professional electronics and IC Mask Design Engineer. I have several years of experience in --- 1. Analog Circuit & Layout Design @TSMC 180/130 nm node 2. Analog/Digital IC Mask Layout @ most advanced node 3. Hspice for post layout simulation and circuit simulation 4. ltspice 5. Magic Layout VLSI tool 6. LASI7 7. Standard cell design and characterization 8. Test chip design. Knock me if you need any help.
Freelancer Electrical Engineers Bangladesh
查看所有Electrical Engineers在Bangladesh

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文件夹

4978537
Differential amplifier layout designed using LASI7 layout tool.
LASI7
Differential amplifier layout designed using LASI7 layout tool.
LASI7
Differential amplifier layout designed using LASI7 layout tool.
LASI7
4620335
4 bit bidirectional shift register design with tanner EDA tools. It can shift data to left and right depending on control circuit
4 bit bidirectional shift register design with tanner EDA
4 bit bidirectional shift register design with tanner EDA tools. It can shift data to left and right depending on control circuit
4 bit bidirectional shift register design with tanner EDA
4 bit bidirectional shift register design with tanner EDA tools. It can shift data to left and right depending on control circuit
4 bit bidirectional shift register design with tanner EDA
4596807
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
4508105
Here 8T SRAM bitcell has been designed using NCSU 15nm FinFET PDK
8T SRAM bit cell design in NCSU 15nm PDK
4161039
long channel band-gap reference circuit has been designed
Bandgap voltage refernce circuit
long channel band-gap reference circuit has been designed
Bandgap voltage refernce circuit
4135315
Here, a cascode amplifier has been designed using Cadence Virtuoso ADE. Small AC signal analysis is performed and Measured AC Gain and Phase Margin
Common Source Common Gate (CSCG) or cascode amplifier
Here, a cascode amplifier has been designed using Cadence Virtuoso ADE. Small AC signal analysis is performed and Measured AC Gain and Phase Margin
Common Source Common Gate (CSCG) or cascode amplifier
Here, a cascode amplifier has been designed using Cadence Virtuoso ADE. Small AC signal analysis is performed and Measured AC Gain and Phase Margin
Common Source Common Gate (CSCG) or cascode amplifier
Here, a cascode amplifier has been designed using Cadence Virtuoso ADE. Small AC signal analysis is performed and Measured AC Gain and Phase Margin
Common Source Common Gate (CSCG) or cascode amplifier
4978537
Differential amplifier layout designed using LASI7 layout tool.
LASI7
Differential amplifier layout designed using LASI7 layout tool.
LASI7
Differential amplifier layout designed using LASI7 layout tool.
LASI7
4620335
4 bit bidirectional shift register design with tanner EDA tools. It can shift data to left and right depending on control circuit
4 bit bidirectional shift register design with tanner EDA
4 bit bidirectional shift register design with tanner EDA tools. It can shift data to left and right depending on control circuit
4 bit bidirectional shift register design with tanner EDA
4 bit bidirectional shift register design with tanner EDA tools. It can shift data to left and right depending on control circuit
4 bit bidirectional shift register design with tanner EDA
4596807
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
8 bit adder was designed in TSMC 180nm with layout having LVS and DRC clean.
8 bit adder
4508105
Here 8T SRAM bitcell has been designed using NCSU 15nm FinFET PDK
8T SRAM bit cell design in NCSU 15nm PDK
4161039
long channel band-gap reference circuit has been designed
Bandgap voltage refernce circuit
long channel band-gap reference circuit has been designed
Bandgap voltage refernce circuit
4135315
Here, a cascode amplifier has been designed using Cadence Virtuoso ADE. Small AC signal analysis is performed and Measured AC Gain and Phase Margin
Common Source Common Gate (CSCG) or cascode amplifier
Here, a cascode amplifier has been designed using Cadence Virtuoso ADE. Small AC signal analysis is performed and Measured AC Gain and Phase Margin
Common Source Common Gate (CSCG) or cascode amplifier
Here, a cascode amplifier has been designed using Cadence Virtuoso ADE. Small AC signal analysis is performed and Measured AC Gain and Phase Margin
Common Source Common Gate (CSCG) or cascode amplifier
Here, a cascode amplifier has been designed using Cadence Virtuoso ADE. Small AC signal analysis is performed and Measured AC Gain and Phase Margin
Common Source Common Gate (CSCG) or cascode amplifier

评论

变更已保存
展示8中的1-5条评论
 筛选评论规则：
5.0
$550.00 USD
Project for Rubel S. -- 3
He did an exceptional work in installing CADENCE for IC Design
Electronics
Verilog / VHDL
Electrical Engineering
PCB Layout
+1更多
S
的国旗 Ahmed A.
@sugarymouth2015
•
3 年前
5.0
$220.00 USD
Project for Rubel S.
He has done good job
Electronics
Verilog / VHDL
Electrical Engineering
PCB Layout
+1更多
S
的国旗 Ahmed A.
@sugarymouth2015
•
4 年前
5.0
$480.00 CAD
Stick diagram of differential Amplifier
An expertise in Cadence platfom, did a great job in time with excellence! He will definitely be my first choice from the very next time onwards for my Cadence projects!
Electronics
Electrical Engineering
Electronic Design
A
Closed User
@amitparekh35
•
5 年前
5.0
$25.00 USD
Install process design kit(pdk) in cadence
Rubel has an excellent background in cadence and how to install kits. Also, he explains and gives you guides to resolve the issues.
Linux
CentOs
A
的国旗 Abdulaziz A.
@abdulazizal10
•
5 年前
5.0
$261.00 USD
design 4-bit shift left and right register using Tanner L-edit
Great guy would work with him again
Microcontroller
Electrical Engineering
PCB Layout
Computer Science
Systems Engineering
Y
的国旗 Patrick L.
@yzahr
•
5 年前

经验

IC Design Engineer

Ulkasemi
5月 2017 - 11月 2017 (6 个月, 1 天)
Working as an IC Design Engineer. Responsible for standard cell development and test chip in advanced node process.

教育

B.Sc in EEE

Ahsanullah Biggyan O Projucti Bishwabiddalaya, Bangladesh 2013 - 2017
(4 年)

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顶级技能

Electrical Engineering 7
Electronics 6
Verilog / VHDL 5
PCB Layout 5
Circuit Design 4

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