CLOCK & DATA (CDR) Recovery Unit
€1000-3000 EUR
货到付款
Qualified and experienced electronics enginner is needed for the following CDR Unit design:
Circuit accepts a modulated (clock and data) signal with a basic frequency of 66MHz and recovers clock and data.
Analog conditioning is HPF/LPF to exclude unwanted frequences, Digital Signal conditioning is given in Differential Equations form for FPGA integration (quite simple).
Slicer picks the decision/slicing level of 'high' and 'low' output. Slicer specs available in analog form, so if not possible to move in digital domain a D/A will also have to be introduced to the circuit.
A block diagram of the project can be found attached.
More details can be discussed under NDA.
项目ID： #6338355
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有13名威客正在参与此工作的竞标，均价€2588/小时
Hello, I am an embedded systems designer and good in dealing with high speed signals like LVDS etc and would love to work on this project. Kindly contact for further conversation and award of project to begin wo 更多
We have done a similar circuit earlier. Do you need a system design as per the specifications. If so with which simulator.
I am a senior electrical engineer with over 10 years of experience. I have experience in analog filter design, A/D converters and digital signal processing. I have produced similar products for the television broadcast 更多
dear sir we have designed bit synchronizer and frame synchronizer and decom cards for PCM telemetery and moreover we have worked on several SDR based systems. we can provide you the best possible solution and can giv 更多
