FPGA serial decoder -- 2

Dear sir, I have more than 7 years experience in digital design using VHDL, I will provide you with the complete working design

hello! please accept my bid to begin working at your project! I want to help you, but the right price for your project is also important! Have a nice day!

Hi, I have a 16+ years experience in FPGA based hardware and logic design. I have used Xilinx, Altera and Lattice FPGAs in my projects. I am also proficient in VHDL and Verilog. SInce I won't have exactly same boar 更多

HI I am an electronic engineer and currently working in a company related to VLSI design. I know all verilog , vhdl and system verlog. I can help you.

Hi Myself Shobhit Kapoor , I have 10+ Years of experience in FPGA/ASIC Design and Verification , will provide you best reats with quality work , I am little new to freelancer.com but have very good reputation in oDesk 更多

Dear! I have three years experience in ASIC field, good command in RTL design and coding with Verilog. I've been working for Dolphin Technology Inc (at San Jose, CA) since I graduated. Currently I'm designing RTL 更多

I have done a lot of work in verilog and I am focusing only on verilog as you can see with my reviews. I will do the best job as it is equally important for me to complete the job and satisfy you to get the good revie 更多

A proposal has not yet been provided

Hello, Pls see attached doc showing my understanding of your requirements in a block diagram. We can do this in verilog/vhdl/mixed (prefer verilog). No way to attach the doc. pls provide you email/skype 更多

Hello There I can complete this job within 6 days. I can write the verilog model and also write testbench using system verilog to verify the RTL model. I will use IUS for functional simulation, My simulator in simvisi 更多

I, Keyur Mahant working in One of the leading University of India as Asst. Professor in Electronics and Communication Engg. And Space Technology Center as Project Scientist in which, I am working on “Single Event Upset 更多

A proposal has not yet been provided

Hi, I have a very good experience in FPGA design and verification. this project requires both design & verification efforts. because verification identifies any corner case or random failures in the design. I ca 更多

A proposal has not yet been provided