VLSI design and testability using SPICE/ Verilog/VHDL
$250-750 USD
货到付款
An applied project may involve using tools such as Spice, Verilog/VHDL, etc. to demonstrate its success
项目ID： #15447244
关于项目
有8名威客正在参与此工作的竞标，均价$482/小时
Hi, I do work as a IC Layout and system design engineer in Bangladesh. Hope I can help you Or, if you need any help regarding IC layout mask design you can contact
Hi Muhammad, my name is Zeeshan. Please share more details of your project. Relevant Skills and Experience I am MS Electrical Engineer and have extensive experience with Spice and verilog. Proposed Milestones $333 US 更多
I need more information on the project task. Relevant Skills and Experience I'm familiar with verilog/verilog-a/verilog-ams and spice. Stay tuned, I'm still working on this proposal.
