I am final year student of Computer Engineering . I have more the 2 year Experience on Computer Architecture. and study the background Course Computer Organization , Microprocessor , Digital System Design and very important computer Architecture. and complete the semester project related to Processor like RISC Procssor, MIPS Processor , Arm Processor . and implement the project on VHDL and Verilog make the synthesis in Xilines for run and test the project on FPGA.