Design and development of CCSDS based Telemetry Encoder on FPGA using VHDL, - open to bidding

The project will comprise of three phases. First phase will be the know how development of CCSDS Packet TM encoding Standard. The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed. Finally all the modules will be integrated as a system in the third phase of the project. Complete working TM Encoder will be demonstrated on FPGA kit.