Simple Verilog Project

$15 USD

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超过 6 年前

$15 USD

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Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3.

Electrical Engineering

Engineering

FPGA

Matlab and Mathematica

Verilog / VHDL

项目 ID: 15393347

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活跃6 年前

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@loi09dt1

A proposal has not yet been provided

$30 USD 在1天之内

4.8

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6.7

@raulbehl

Hey! Please check my reviews and profile to know more about me and my work. Thank you!

$20 USD 在4天之内

5.0

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5.8

@iZoneFreelancer

Have worked on similar projects using VHDL & Verilog. So, can do it. Relevant Skills and Experience Relevant Skills: 1. Verilog & VHDL Proposed Milestones $50 USD - Completion More details about the requirement.

$50 USD 在10天之内

3.5

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2.9

@prakashddit

have 3+ years of expertise

$20 USD 在1天之内

4.6

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2.0

@davidkarani

I request for this job humbly and i will do it on time

$20 USD 在3天之内

0.0

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0.0

@Ramvenkat111

Hai, I have 4 years of experience in FPGA design and validation. Handled complex projects on image processing and signal processing. Feel free to contact any time. Thankyou.

$20 USD 在10天之内