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Restructuring and Code Conversion

$3000-5000 USD

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已发布超过 4 年前

$3000-5000 USD

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I need parse Verilog (vhdl) code for fpga, structure the same code and rewrite to another fpga. The project is ready.
项目 ID: 21779876

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活跃4 年前

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11威客以平均价$3,727 USD来参与此工作竞价
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Dear sir I have more than 10 years experience in digital design using vhdl and verilog please message me so that we can discuss
$3,000 USD 在5天之内
4.9 (503条评论)
8.2
8.2
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Hi there, I have read your project description and i'm confident i can do this project for you perfectly.I still have a few questions. please leave a message on my chat so we can discuss the budget and deadline of the project. Thanks
$4,000 USD 在7天之内
4.8 (99条评论)
7.9
7.9
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Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.
$3,000 USD 在15天之内
4.9 (94条评论)
6.9
6.9
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Hi I have been working on Verilog-VHDL and Xilinx and Altera FPGAs by more than 6 years. Please let me know your exact requirements, I can work on it. The price mentioned is negotiable according to your requirements. Thanks
$3,000 USD 在5天之内
4.8 (33条评论)
6.1
6.1
用户头像
Hello If I understand you correctly, you need to port some Verilog and VHDL to another FPGA. I have over 10 years experience in developing with FPGA devices, so dont see a problem in doing that. The bid amount is just a place holder as it may be I can reduce my bid once I know how much work is involved. Regards Jon
$4,000 USD 在7天之内
5.0 (4条评论)
4.5
4.5
用户头像
hello ! I have gone through your job posting and become very much interested to work with you. I am an expert in this field. I have already completed several projects like this. Awaiting an affirmative response from you!
$4,000 USD 在15天之内
0.0 (0条评论)
0.0
0.0
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Hi,dear. I am a senior software developer. I have just checked your project description, I am able to complete this project. I am looking forward to your response. Thanks.
$4,000 USD 在30天之内
0.0 (0条评论)
0.0
0.0
用户头像
Hello. I love working with FPGAs! I can only guess at the complexity of the project based on your suggested bid range, but please contact me so we can talk more. It may not be as complicated as you think.
$5,000 USD 在10天之内
0.0 (0条评论)
0.0
0.0
用户头像
An Embedded Software/Hardware engineer with a demonstrated history of working experiences in the top rated communication industries. Skilled in RTL Languages (VHDL/Verilog), C++, Visual C++, Matlab, web application design with JavaScript, and Network simulators. My main work direction was on implementation of Digital Signal Processing and Optical and Wireless Communication systems. Graduated from Sharif University of Technology (Highest ranked Technological University among all Iran's universities). Currently works as a Postdoc Fellow at University of Waterloo in K/W area, Ontario, Canada.
$3,000 USD 在14天之内
0.0 (0条评论)
0.0
0.0

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São Carlos, Brazil
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