Design a16-bit RISC MIPS Processor using verilog and implementing on FPGA board

Dear sir I have more than 9 years experience in digital design using verilog please check my profile also please message me so that we can discuss

Hello! Please check my reviews to know a bit about me. I have designed such processors before and would be okay to do that again. Thanks!

I am an Electrical Engineer having specialization in Electronics and Control, teaching in Electrical Department at FAST National University Pakistan. I am also persuing my MS degree in Electrical Engineering with specialization in CONTROL. I have taught the followings courses, and also done many projects related to these subjects as well as related to consumer electronics products. 1. Control System Design & Modelling (Continuous, Discrete, Linear, Non-Linear, Optimal, Fuzzy Logic + Matlab & Simulink) 2. Digital System/Logic Design (Verilog, VHDL, Logisim) 3. Micro-controllers (8051, Arduino, PIC) 4. Power Electronics (PSIM, MATLAB, PSpice) 5. Control of Electric Machine Drives 6. Circuit Analysis and Designe etc 7. PCB Design (Proteous + Ultiboard + Altium Designer) I assure you, if you assign your project to me, you surely gonna work with me in future. Note: I also provide Online or Recorded Video Tutorials to the online students for Electrical Engineering Subjects.

Hi , I am working as FPGA design engineer since last 7 years and I have expertise in both verilog and VHDL. I can help you in this project with greater accuracy. Hi , I am working as FPGA design engineer since last 7 years and I have expertise in both verilog and VHDL. I have worked on RISC project before. I can help you in this project with greater accuracy.

hi i have done similar work earlier . you can check my reviews. other technical discussion on chat . regards

i will realse with a piece of code that run as assembly program. i already done mips single cycle risc last week. please tell me in detail that your architecture is pipeline or not. we will satisfy you.

Project cost would be 10000 rs. pay 2000 on freelancer, remaining direct transfer Providing service in academic, project, training, coaching in VHDL, VerilogHDL since 2009. Experience of completing projects on Quartus, Xilinx, Modelsim, NIOS II. Worked on real hardware projects implementation on MaxII, Cyclon, Spartan, DE1 Boards of Altera, Spartan Board of Xilinx. Completed projects on the field of VGA, SDRAM/SRAM Controller, I2C, UART, SPI, External hardware interfacing. published 2 research papers on IEEE. I assure you would be services with satisfactory and successfully project completion within time limit.

I start working on the project as you select me as provider. I will deliver the code as you create the requested milestone. Regards, Botond

Will provide: - Core in Verilog - Testbench in Verilog - Assembler in Perl/Python - 10 code testcases Included in the price can be AHB or AXI buses if needed

A proposal has not yet been provided

Hi, Iam a open source contributor worked alot on RISC-V (rocket core) as a part of the GSoC Programme. I will happily work on this if I get a chance. I have a good skill set with Verilog (built so many core). Being a Under-Graduate from International Institute of Information Technology, I have worked a lot on Verilog till past three years.

i have already done a similar project successfully and implemented that on xilinx fpga and altera fpga kits. i have years of experience in hdl coding. i hope we can work together for this project and complete this within 3-5 day. (additional days are for testing on your board ). you can pay only after the result