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CPLD converter, dual I2S codecs to TDM

$30-250 USD

已完成
已发布大约 4 年前

$30-250 USD

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The project's goal is to have two I2S codecs, both at the same samplerate, selectable 48/96/192KHz, connected to a CPLD and the CPLD to provide a TDM protocol for connection to a MCU. Codecs will have 48/96/192KHz, stereo, 32bits sample depth and will work at I2S protocol. Codecs will perform both capture and playback concurrently. The TDM protocol should have 4 slots for channels. Some points that need to be taken into consideration in order to better understand the requirements: 1. the freelancer must have good kowledge of audio TDM and I2S protocols. 2. The freelancer should decide what CPLD is most appropriate and cost beneficial to the task, CPLD has to be a member of Intel/Altera MAX V CPLD. 3. The freelancer will provide appropriate testbech to verify the proper behaviour of the design with written instructions on how to perform the tests. 4. The freelancer should provide all the sources and the complete Quartus project.
项目 ID: 24754472

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活跃4 年前

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Hi, I have good knowledge I2S, Audio TDM/PCM signal. I have extensive experience in hdl coding in Max V CPLDs of Intel. Please ping me to discuss further. Regards, Chhanda
$150 USD 在3天之内
5.0 (19条评论)
5.1
5.1
3威客以平均价$172 USD来参与此工作竞价
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Dear sir I have more than 10 years experience in FPGA and CPLD design and i have experience in working with intel MAX family, I can do the required design and provide the test benches, please message me so that we can discuss
$167 USD 在7天之内
4.9 (508条评论)
8.1
8.1
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I am an EE engineer. I have lots of experience designing circuitry in both digital and analog circuits and in programming field worked with Xilinx and Altera FPGA boards writing VHDL and embedded C for NIOS II (field of interest). I have a background in digital design. I also worked with microcontrollers such as MSP430, Arduino, PIC, etc with both Assembly and C language . ABOUT YOUR PROJECT, as this is a VHDL code I will always testbench my codes before sending it to my clients you may want to get your output from GPIOs (PIO in Altera family fpgas) or the available output on the board which is a place of discussion. All the protocols like UART, I2C or in your case I2S does follow pretty the same principle which is the sending or receiving with acknowledgements in between. I have done lots of similar projects before and can handle your project easily. We can discuss it more over chat. Regards,
$200 USD 在10天之内
5.0 (48条评论)
6.3
6.3

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GREECE的国旗
Athens, Greece
4.9
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会员自1月 21, 2010起

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