Vlsi testing and verification using Synopsis EDA for sequential circuits

Dear sir I have more than 10 years experience in digital design using FPGA and VLSI design, I suggest creating AES circuit available in IEEE paper, and perform testing and simulation Best regards

Hello! Please check my reviews and profile to know more about me and my work. Hope you’d contact to discuss further. Thank you!

hi, i can help you in VLSI testing project and sequential circuit design Relevant Skills and Experience Electrical Engineer Proposed Milestones $500 USD - Sequential Circuit Desgin

have expertise in RTL Digital Logic Design for 2.5+ years

We have experienced in Synopsys EDA tools and we have access to the licensed tools to carry out the task. Relevant Skills and Experience Verilog, VHDL, Design Compiler Primetime VCS Formality RTL Desing and Verification FPGA - Xilinx, Altera Proposed Milestones $666 USD - Deliverables Will be given based on the project Additional Services Offered $200 USD - Custom Board design $100 USD - ATE , Test JIG PC tools creation for demo

I have well experienced in doing such kind of jobs........................ Relevant Skills and Experience verilog/vhdl Proposed Milestones $700 USD - i will do my level best

I expert in VCS. ReWrite your design in System Verilog. Time deponds on your project.