I am looking for someone to develop a project that will allow data to be transmitted from my Field Programmable Gate Array (FPGA) to a PC. The connection type that should be used is USB and the language used to communicate must be Verilog. Data that needs to be transmitted is text only. I need a detailed solution that can handle transmission of data in a smooth, consistent manner. It should be able to identify events and their associated data while being reliable and efficient. The hardware and software involved should be thoroughly tested and debugged. The solution should also be documented and include any necessary reports/specifications. The project should be delivered in a timely fashion.
I am looking for a freelancer to design a single clock process based on RISC-V ISA using Verilog. The clock process design must have the following specific features and functionalities: The project only requires the implementation of the base RISC-V ISA, without any specific extensions. The ideal freelancer must be skilled and experienced in Verilog and have a deep understanding of RISC-V ISA. Additionally, I would prefer someone who has previously worked on similar projects and can provide examples of their work.
Hi there Im looking for some ideas for a large stickers I can put on my car that will be catchy and will stand out. Its the name of my new youtube channel which will be used for off road adventures in Australia. I want a sign that will pop and be eye catching. Th e Name of my channel are "Voetspore through OZ" and I was thinking to have the name incorpated on Tyre track prints as the background of the name. Im open to colour selection. I have uploaded photos of the car so we can see how it will look on the car. These pics I have attached is only for the idea that we like but please be creative and lets creative something amazing.
I am looking for a freelancer who can help me find a behavioral module that incorporates all of the methods used to implement true addition and true subtraction with a test bench module. The ideal candidate should have experience in Verilog and be able to work on a project with some design preferences. The test bench module should have a basic level of complexity.
I am looking for a freelancer to design a gas detector circuit using Verilog for the Basys 3 board. The detector should be able to sense Carbon Monoxide gas. I have a rough idea of what I want. The buzzer alarm does not have any specific requirements, but it should be loud enough to be heard. The ideal skills and experience for this job include proficiency in Verilog, knowledge of gas detection circuit design, and experience with the Basys 3 board.
I need to control the buck converter using a current mode control in digital form. That means i need to use digital PI, ADC converter, Digital PWM. For these digutal controlling parts I have to write verilog codes or have to use IP's in vivado to implement on FPGA. At the end I need to do PCB design for the buck converter and after that I have to combine them and observe the results on oscilloscope.
Hello! I am in need of a freelancer to help me with a project creating a car elevator controller. The controller will be created using Vivad Verilog code and fpga implementation. I am looking for someone who can provide a detailed project proposal in their application. It is also important they have past work and experience in the same field. I won’t need any type of remote access for this project so please do not include any advice on that as part of your proposal. If you believe you are suited for this project and would be interested in working with me, please apply and include your detailed project proposal. I look forward to hearing from you!
I am looking for help with creating a System Verilog code for a sequential multiplier and a floating point multiplier. For the multiplier, I would need both types: sequential and floating point. The verification of the functionality is required. I am necessary looking for an experienced engineer who truly understands what's needed for this requirement and can efficiently and quickly develop the code for it.
As part of a development project, I need help designing verilog code on Xilinx. I'm looking for experienced freelancers with the technical skills to properly implement the design. I need complete control when it comes to providing feedback and making sure the progress is on track. The right candidate should have a solid track record and demonstrate their expertise in the same field before applying to the job.
I'm looking for a VHDL 1st-in 1st-out (FIFO) project to be completed. I need a Verilog code to complete the FIFO example. Also, syntax is very important, therefore, I am attaching an example (LIFO) to illustrate the syntax.
Looking for a GoLang Developer with experience on following GO concepts (Gorilla Mux, GIN, Slices, Maps, Structs, Interfaces, GoRoutines, GoKit, Go-Hystrix, Godoc, Godep, GO Modules etc) And Past experience on any GOLANG Project
write a verilog code for a straight line equation y=mx+c where all m,x and c are 32 bit and even after arithmetic operations between m,x,cand y the final values should always be truncated to 32 bit(for example m*x gives a 64 bit value which has to be truncated to 32 bit after the multiplication) . The final value should be in 4.28 format [i.e.,4 for integer part and 28 for decimal part(fractional part)] . In the integer part one bit will be for sign and there are left with 3 more bits which can have a maximum value till 7, and the decimal part consists of 28 bits ,so the value will be + or - 7.9 for 4.28 m and x should take decimal values
I need to use GitLab CI to check for students' work assignment (language VHDL (run with GHDL) if that matters). The idea is that I have a "secret" testbench, which is compiled with student's code (submitted as git commit to GitLab), and the job needs to check if the submission passes the test. There must be zero possibility for the student to misuse the GitLab to get access to the secret code. Preferably the secret code is stored and run in a separate computer (than gitlab-runner). Deliverables: - Description how the objectives are met - Installation instructions (if any) - Example project with CI pipeline - Source codes of customized scripts / code (C or C++ allowed). Please note: - GitLab CI allows to run arbitrary code in the CI-job, thus the student wi...
BCD multiplier development using Verilog HDL for Xilinx FPGA technology Input/Output Format: - Desired input/output format is Binary Testbench: - Testbench required for the Verilog code Ideal Skills and Experience: - Proficiency in Verilog HDL - Experience in BCD multiplier development - Expertise in Xilinx FPGA technology - Familiarity with Binary input/output format - Ability to create a testbench for Verilog code Goals: - Develop a functional BCD multiplier using Verilog HDL - Ensure the Verilog code passes the testbench - Optimize the design for Xilinx FPGA technology.
Design a push-button door lock that uses a standard tele-phone keypad as input.
...this plug-in is to provide a front-page to a student to get all column data (total 10 columns) based on the 4-column filtering these students provide (). I would therefore suggest if the mentioned code snippet is what I have demanded? If not, I would prefer the freelancer to provide his/her own amendments in this code to fulfil my objective. Second, he/she is required to provide me testbench to test the filteration process such that I am able to download the CSV file filtering the data based on the required 4 search filters. Note1: My ultimate goal is to design a wordpress website where I must put this javascript plugin. However, in this task, I just need a javascript code snippet. Note2: I would like the freelancer to convert the into file in order for
Hello! I am looking for an experienced Electronics Engineer with a strong background in ...strong background in Xilinx ISE and a good report writing skill. The job duration is a short-term period that is less than 1 month. Expert level programming knowledge is required as well as technical document assistance. If this job opportunity is of interest, please do not hesitate to reach out! I look forward to hearing from you. The task is to Simulate a design with the aid of a “graphical testbench” (also known as a “Test Bench Waveform” file), using the Xilinx ISE v10.1.03 software. You must set the colour scheme of your simulation waveforms to the "Classic" colour scheme, via the ‘Edit’ → ‘Preferences...’ → ‘ISE ...
using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C
I need a full verliog code that will output a "32-bit microprocessor using an FPGA board" 1. High level text description to describe HOW you are implementing your project. 2. DETAILED Block Diagram(s) showing design and detailed interconnections. 3. List of tasks completed 4. List of things I need to simulate, debug, and demonstrate 5. Data sheets for each IC used in your design. 6. Worst Case analysis - show tables / spread sheets in progress in process for Noise margin, Loading, Timing 7. I WILL NEED A VIDEO EXPLAINING HOW THE CODE WORKS (IN ENGLISH) 8. ALSO PICTURES OF THE CODE RUNNING SMOOTHLY NO PLAGIARISM PLEASE PLEASE COME UP WITH YOUR OWN CODE
We are Hiring Technical expert (Xilinx Vivado) Position: Academic Technical expert Freelancer Experience: 2+ years Qualification: Masters or Doctorate in Electronics & Communication Engineering Skills Required: Turbo Decoder VLSI Xilinx Vivado FPGA Verilog Machine learning Specific area: Need a Verilog, Xilinx Vivado and Machine learning expert Time: Part-time/Freelance Job Description: Require a Freelancer, who can do coding will be done on Xilinx Vivado. Implementation will be done on FPGA using Verilog/ system Verilog language
...candidates should include past work in their application and provide relevant experience related to this project. Any working code previously developed is a plus. Deadline for the delivery 20th April 2023. A quotation is required, together with the proof of previous expertise of the working code already developed It will be required to 1. deliver VHDL source code for LIN master bus controller 2. testbench with a Verification module, or any other sort of mechanism to emulate a node 3. Integration and testing of a simple test code on hardware provided by us 4. documentation...
Looking for a partner to consult on design/build of HART AI/AO gateway/multiplexor. Please do not respond if you do not have 1 year hands on experience with this domain. Design/build a HART gateway HAT for RPi (& its variants) with signal pass-thru (both in/out), supporting HART/IP, WirelessHART, ISA100 Wireless, MBTCP server. Only 1 type service at a time. The server shall support multiple (min 8) managed connections. There should be min 8 AI channels on HAT, each supporting HART multi drop and standard 4-20mA inputs. The DD/EDDL/FDI file types of HART device vendors shall be supported. PACTWARE compatible & multiple stackable HATS. The use of pins of RPi must be approved by us. you may use existing dev kits from analog devices, ST, Microchip etc., but ensure the ready availabil...
Europe, Italy timezone preferred. Lead the activity for porting FPGA design to Silicon technology (memory replacement, ...) Carry on simulations of the updated RTL design to check that the functionality remains unchanged Execute static and formal verification of RTL code using appropriate tools Run trial synthesis on the RTL design and check the timing violations Lead the act...tools Run trial synthesis on the RTL design and check the timing violations Lead the activities for SoC sub-block Static Timing Analysis. Required Skills (expert): VHDL language Digital ASIC design flow Use of digital simulations with standard industry simulators (Mentor QuestaCore) Static and formal RTL verification (e.g. Synopsys Spyglass) Synthesis tools (e.g. Cadence Genus) UVM and System Verilog test...
Hi, can you help me out to code Verilog coding for the sound detection sensor for turning on the LED on DE1 SoC Cyclone V board?
Hi Ahmed K., I noticed your profile and would like to ask for help with debugging a verilog project. We can discuss any details over chat.
Hi Sardar Hasnain A., I noticed your profile and would like to ask for help debugging a verilog project on vivado. We can discuss any details over chat.
Turbo codes are error correction codes that are widely used in communication codes exhibits high error correction capability as compared with other error correction codes. This paper proposes a Very Large Scale Integration (VLSI) architecture for the implementation of Turbo decoder. Soft-in-soft out decoders, interleavers and deinterleavers is used in the decoder side which employs Maximum-a-Posteriori (MAP) algorithm. The number of iterations required to decode the information bits being transmitted is reduced by the use of MAP algorithm. For the encoder part, this paper uses a system which contains two Recursive convolutional encoders along with pseudorandom interleaver in encoder Turbo encoding and decoding is done using Octave, Xilinx Vivado, Cadence system is implemented and synthe...
Replace fiber framework into pdf with mux framework
Project to be created in Altium Designer - Pcb is simple breakout board using MUX switch CD74HC4067 -(The CD74HC4067 is a 16-Channel Analog Multiplexer/Demultiplexe) The outputs are being routed to the jst Connectors. DFX outline for file will be supplied.
I want someone who understands FPGA, Vivado, Verilog, VHDL etc for a report
Hi, How are you doing. I am looking for electrical engineers to work on multiple tasks in following areas: • Embedded C Programming. • VHDL/Verilog, LABView/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. I am looking for long term work relationship. New freelancers are warmly welcomed. Important Note: I need dedicated freelancers who strictly follow the deadline and give me good quality work without any plagiarism.
Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.
...generator, where scanline parameters are passed as input wires : scanline color, scanline thickness, scanline interval 5. output is overlayed by the bitmap OSD with the same resolution as output format Requirements : aside from the DDR memory interface, or PLL no vendor or encrypted IP blocks can be used, for example no Altera/Intel video pipeline. Everything must be in written verilog source code. Must include verilog testbench that will accept input picture(in any format) and produce resulting picture(in any format). suggested pipeline i/o ports: Sysclk, [23:0] RGBin, HSin,VSin,DEin, Clkin [23:0] RGBout, HSout, VSout, DEout, Clkout [31:0] parameters[0:...] (whatever count is required). all needed memory interfaces signals to the memory multiplexer. Any dev b...
...create a verilog code for image dehazing. The image is converted into a text file using Matlab(all pixel values are converted into corresponding hexadecimal values). This text file is given as the input to the verilog program. First we need to find the minimum of RGB value of each pixel and create a matrix. Then we need to consider a small window/mask in the new matrix and find the minimum of that mask and sweep the mask through the entire new matrix to create the darkchannel image. Then by using the equations using the darkchannel prior algorithm we need to recreate a haze free image. (the output of the verilog code will be a text file and is recreated into an image using Matlab. I am attaching a reference paper. I just need to get the basic dehazing part fro...
I need code for my bot who follow the given line using line sensor. this code should be written in verilog language and fpga cyclone 4 is used as board.
dark channel prior basically computes the minimum of rgb values present in a single pixel and assigns that value to the pixels. Once that is done, a patch of pixels is taken and the minimum is taken after which all the pixels in that patch are assigned the new minimum value. The input is a hex file of coloumn form and output is another hex file
I am a verification engineer in Bangalore India, and preparing for Top Semiconductor Companies Interview Process like INTEL, NVIDIA , GOOGLE , Qualcomm, NXP Semiconductors , SAMSUNG and many more etc. So I am looking for a verification expert ...showcase me your skills . So that after gaining knowledge with your help I can crack any company interviews . I want all types of problem solving questions to be covered including puzzles as well . Kindly ping me here if you help me out with above . Kindly provide all types of possible questions which a company can ask in a interview , I need a kind of Question Bank. Mandatory Skills : Verilog , System Verilog, UVM , Functional Coverage , Code Coverage , Assertions , Constraints , Digital Electronics and FSM problem Solving questi...
In this project students are aske...the required form. It is important to convert the floating-point format of the coefficients to an integer format and other operations such as multiplication and addition must consider this conversion process as well. It is required from the group to do the following 1- Develop the C and the VHDL code, to be run both in NIOS II. 2- Test the VHDL code in ModelSim using testbench. The student is required to develop the testbench VHDL code. Also, to generate a run with arbitrary values for inputs for testing purpose. 3- Use the Quartus beside the Platform (Qsys) applications to develop the Nios II processor and the custom XTEA hardware accelerator interfaced together. 4- Measure comparatively the time it takes to compute a 32rounds of XTEA encr...
Two tasks based on verilog, serial adder and RTL for APB based protocol. More information will be shared later. Deadline - 2days[maximum] Price - 75AUD
Im working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM
Im working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM
1) Frequency divider by - / 2n - / by any integer 2) Serial Peripheral Interface (SPI) - Both master and slave 3) UART TX/RX - Asynchronous serial communication - Start bit, Stop bit, over sampling etc. - Exercise on cross-clock domain synchronizer What to submit - RTL code (.v) with inline comment - Test bench (.v) with inline comment - Timing diagram (gtkwave) with annotation - Rough description of the corresponding circuit Quick turnaround needed
Need a System Verilog Expert for digital logic circuit design
We need to program a FPGA board using verilog code with XNOR, Multiply, shiftleft and add modules that can run on the board using different switches. When we compile the code there are no errors but when we try to put the code onto the board it is showing only zeros so we think that there is something wrong with the XNOR, Mul, shiftleft or ADD modules. I will attach all codes and the manual for the project below, thanks.
Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.
The entire description of the project is in the file below Circuit modeling in
Need to implement Pmod MAXSONAR on Arty A7-35T board
